MAX5078
4A, 20ns, MOSFET Driver
10
Maxim Integrated
Use the following PC board layout guidelines when
designing with the MAX5078A/MAX5078B:
• Place one or more 0.1µF decoupling ceramic
capacitors from V
DD
to GND as close to the device
as possible. Connect V
DD
and GND to large copper
areas. Place one bulk capacitor of 10µF (min) on
the PC board with a low resistance path to the V
DD
input and GND of the MAX5078A/MAX5078B.
• Two AC current loops form between the device and
the gate of the driven MOSFET. The MOSFET looks
like a large capacitance from gate to source when the
gate pulls low. The active current loop is from the
MOSFET gate to OUT of the MAX5078A/MAX5078B,
to GND of the MAX5078A/MAX5078B, and to the
source of the MOSFET. When the gate of the MOSFET
pulls high, the active current is from the V
DD
terminal
of the decoupling capacitor, to V
DD
of the
MAX5078A/MAX5078B, to OUT of the MAX5078A/
MAX5078B, to the MOSFET gate, to the MOSFET
source, and to the negative terminal of the decoupling
capacitor. Both charging current and discharging
current loops are important. Minimize the physical dis-
tance and the impedance in these AC current paths.
• Keep the device as close to the MOSFET as possible.
• In a multilayer PC board, the inner layers should
consist of a GND plane containing the discharging
and charging current loops.
• Pay extra attention to the ground loop and use a
low-impedance source when using a TTL logic-
input device. Fast fall time at OUT may corrupt the
input during transition.
Exposed Pad
The TDFN-EP package has an exposed pad on the bot-
tom of its package. This pad is internally connected to
GND. For the best thermal conductivity, solder the
exposed pad to the ground plane in order to dissipate
1.9W. Do not use the ground-connected pad as the
only electrical ground connection or ground return. Use
GND (pins 2 and 3) as the primary electrical ground
connection.
