PIC16(L)F183XX
DS40001744C-page 16 2014-2016 Microchip Technology Inc.
TABLE 8: 20-PIN ALLOCATION TABLE (PIC16(L)F18344)
I/O
(2)
20-Pin PDIP/SOIC/SSOP
20-Pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 19 16 ANA0 — C1IN0+ — DAC1OUT — — — — — — — —
—
IOCA0 Y ICDDAT/
ICSPDAT
RA1 18 15 ANA1 VREF
+
C1IN0-
C2IN0-
—DAC1REF+— —— — — ————IOCA1 Y ICDCLK/
ICSPCLK
RA2 17 14 ANA2 VREF- — — DAC1REF- — T0CKI
(1)
CCP3
(1)
— CWG1
(1)
CWG2
(1)
—
—
CLCIN0
(1)
— INT
(1)
IOCA2
Y —
RA3 4 1 — — — — — — —— — — ————IOCA3 Y MCLR
VPP
RA4 3 20 ANA4
— — — — —
T1G
(1)
T3G
(1)
T5G
(1)
SOSCO
CCP4
(1)
— — — — — —
IOCA4 Y CLKOUT
OSC2
RA5 2 19 ANA5 — —— — —T1CKI
(1)
T3CKI
(1)
T5CKI
(1)
SOSCIN
SOSCI
—— ————
— IOCA5 Y CLKIN
OSC1
RB4 13 10
ANB4 — — — — — — — — — SDI
(1)
SDA
(1,3,4)
—
CLCIN2
(1)
— IOCB4 Y —
RB5 12 9ANB5— — — — — — — — — — RX
(1)
DT
(1)
CLCIN3
(1)
—IOCB5Y —
RB6 11 8
ANB6 — — — — — — — — — SCK
(1)
SCL
(1,3,4)
— — — IOCB6 Y —
RB7 10 7ANB7— — — — — — — — — —
TX
(1)
CK
(1)
——IOCB7Y—
RC0 16 13 ANC0 — C2IN0+
— — — — — — — — — — —
IOCC0 Y —
RC1 15 12 ANC1 — C1IN1-
C2IN1-
—— ————————— IOCC1 Y —
RC2 14 11 ANC2 — C1IN2-
C2IN2-
— — MDCIN1
(1)
— — — — — — — —
IOCC2 Y —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I
2
C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.