2014-2016 Microchip Technology Inc. DS40001744C-page 21
PIC16(L)F183XX
RC3 7 4 ANC3 — C1IN3-
C2IN3-
——MDMIN
(1)
— CCP2
(1)
— — — — CLCIN1
(1)
— IOCC3 Y —
RC4 6 3
ANC4 — — — — — — — — — — — —
— IOCC4 Y —
RC5 5 2 ANC5 — — — — MDCIN2
(1)
— CCP1
(1)
——————IOCC5 Y —
RC6 8 5 ANC6
— — — — — — — — —
SS
(1)
— — — IOCC6
Y
—
RC7 9 6 ANC7 — — — — — — — — — — — — — IOCC7 Y —
VDD 1 18
— — — — — — — — — — — — — — — —
VDD
VSS 20 17 — — — — — — — — — — — — — — — — VSS
OUT
(2)
— — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A
CWG2A
SDO1
SDO2
DT
(3)
CLC1OUT CLKR — — —
— — — — C2OUT — — — — CCP2 PWM6 CWG1B
CWG2B
SCK1
SCK2
CK CLC2OUT — — — —
— — — — — — — — — CCP3 — CWG1C
CWG2C
SCL1
(3)
SCL2
(3)
TX CLC3OUT — — — —
— — — — — — — — — CCP4 — CWG1D
CWG2D
SDA1
(3)
SDA2
(3)
—CLC4OUT— — — —
TABLE 10: 20-PIN ALLOCATION TABLE (PIC16(L)F18346) (CONTINUED)
I/O
(2)
20-Pin PDIP/SOIC/SSOP
20-Pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I
2
C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.