2014-2016 Microchip Technology Inc. DS40001744C-page 1
PIC16(L)F183XX
Description
PIC16(L)F183XX microcontrollers feature Analog, Core Independent Peripherals and communication peripherals,
combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The
Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-Bit Timers
• Up to Three 16-Bit Timers
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection
Memory
• Up to 28 KB Program Flash Memory (PFM)
• Up to 2 KB Data SRAM Memory
• 256B of EEPROM Data Flash Memory (DFM)
• Direct, Indirect and Relative Addressing modes
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF183XX)
- 2.3V to 5.5V (PIC16F183XX)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
eXtreme Low-Power (XLP) Features
• Sleep mode: 40 nA @ 1.8V, typical
• Watchdog Timer: 250 nA @ 1.8V, typical
• Secondary Oscillator: 300 nA @ 32 kHz
• Operating Current:
- 8 uA @ 32 kHz, 1.8V, typical
- 37 uA/MHz @ 1.8V, typical
Power-Saving Functionality
• Doze mode: Ability to run the CPU core slower
than the system clock used by the internal
peripherals
• Idle mode: Ability to put the CPU core to sleep
while internal peripherals continue operating from
the system clock
• Sleep mode: Lowest Power Consumption
• Peripheral Module Disable: Peripheral power
disable hardware module to minimize power
consumption of unused peripherals
Digital Peripherals
• Configurable Logic Cell (CLC):
- Up to four CLCs
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Up to two CWGs
- Multiple signal sources
• Up to Four Capture/Compare/PWM (CCP)
modules
• PWM: Two 10-bit Pulse-Width Modulators
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
- Input Clock: 0 Hz < F
NCO < 32 MHz
- Resolution: F
NCO/2
20
• Serial Communications:
- SPI, I
2
C, EUSART
- RS-232, RS-485, LIN compatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
Full-Featured, Low Pin Count Microcontrollers with XLP Product Brief
