PIC16LF18324-I/ST Datasheet PIC16LF18323-I/JQ, PIC16F18344-I/GZ, PIC16F18344T-I/GZ | P10-P12

PIC16(L)F183XX

DS40001744C-page 10  2014-2016 Microchip Technology Inc.

TABLE 5: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324)

I/O

(2)

14/16-Pin PDIP/SOIC/TSSOP

16-Pin UQFN

ADC

Reference

Comparator

NCO

DAC

DSM

Timers

CCP

PWM

CWG

MSSP

EUSART

CLC

CLKR

Interrupt

Pull-up

Basic

RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — — — —

—

IOCA0 Y ICDDAT/

ICSPDAT

RA1 12 11 ANA1 VREF+ C1IN0-

C2IN0-

—DAC1REF+— —— — — ————IOCA1 Y ICDCLK/

ICSPCLK

RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI

(1)

CCP3

(1)

— CWG1

(1)

CWG2

(1)

—

— — — INT

(1)

IOCA2

Y —

RA3 4 3 — — — — — — —— — — ————IOCA3 Y MCLR

VPP

RA4 3 2 ANA4

— — — — —

T1G

(1)

SOSCO

— — — — — — —

IOCA4 Y CLKOUT

OSC2

RA5 2 1 ANA5 — —— — —T1CKI

(1)

SOSCIN

SOSCI

—— ———

CLCIN3

(1)

— IOCA5 Y CLKIN

OSC1

RC0 10 9 ANC0 — C2IN0+

— — — T5CKI

(1)

— — — SCK

(1)

SCL

(1,3,4)

— — —

IOCC0 Y —

RC1 9 8 ANC1 — C1IN1-

C2IN1-

— — — — CCP4

(1)

——SDI

(1)

SDA

(1,3,4)

— CLCIN2

(1)

— IOCC1 Y —

RC2 8 7 ANC2 — C1IN2-

C2IN2-

— — MDCIN1

(1)

— — — — — — — —

IOCC2 Y —

RC3 7 6 ANC3 — C1IN3-

C2IN3-

——MDMIN

(1)

T5G

(1)

CCP2

(1)

——SS

(1)

— CLCIN0

(1)

— IOCC3 Y —

RC4 6 5

ANC4 — — — — —

T3G

(1)

— — — — TX

(1)

CLCIN1

(1)

— IOCC4 Y —

RC5 5 4 ANC5 — — — — MDCIN2

(1)

T3CKI

(1)

CCP1

(1)

———RX

(1)

(1,3)

——IOCC5 Y —

VDD 1 16

— — — — — — — — — — — — — — — —

VDD

VSS 1413——— — — — —— — — ——————VSS

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: These pins are configured for I

C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

 2014-2016 Microchip Technology Inc. DS40001744C-page 11

PIC16(L)F183XX

OUT

(2)

— — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A

CWG2A

SDA

(3)

CK CLC1OUT CLKR — — —

— — — — C2OUT — — — — CCP2 PWM6 CWG1B

CWG2B

SCL

(3)

CLC2OUT — — — —

— — — — — — — — — CCP3 — CWG1C

CWG2C

SDO TX CLC3OUT — — — —

— — — — — — — — — CCP4 — CWG1D

CWG2D

SCK — CLC4OUT — — — —

TABLE 5: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) (CONTINUED)

I/O

(2)

14/16-Pin PDIP/SOIC/TSSOP

16-Pin UQFN

ADC

Reference

Comparator

NCO

DAC

DSM

Timers

CCP

PWM

CWG

MSSP

EUSART

CLC

CLKR

Interrupt

Pull-up

Basic

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: These pins are configured for I

C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

PIC16(L)F183XX

DS40001744C-page 12  2014-2016 Microchip Technology Inc.

TABLE 6: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18325)

I/O

(2)

14/16-Pin PDIP/SOIC/TSSOP

16-Pin UQFN

ADC

Reference

Comparator

NCO

DAC

DSM

Timers

CCP

PWM

CWG

MSSP

EUSART

CLC

CLKR

Interrupt

Pull-up

Basic

RA0

13 12 ANA0

—

C1IN0+

—

DAC1OUT

— — — — —

SS2

(1)

— —

—

IOCA0

Y ICDDAT/

ICSPDAT

RA1 12 11 ANA1 VREF

C1IN0-

C2IN0-

—DAC1REF+— — — — — — — — —IOCA1 Y ICDCLK/

ICSPCLK

RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI

(1)

CCP3

(1)

— CWG1

(1)

CWG2

(1)

—

— — — INT

(1)

IOCA2

Y —

RA3 4 3 — — —— — — —— — — ————IOCA3 Y MCLR

VPP

RA4 3 2 ANA4

— — — — —

T1G

(1)

SOSCO

— — — — — — —

IOCA4 Y CLKOUT

OSC2

RA5 2 1 ANA5 — —— — —T1CKI

(1)

SOSCIN

SOSCI

—— ———

CLCIN3

(1)

— IOCA5 Y CLKIN

OSC1

RC0 10 9 ANC0 — C2IN0+

— — — T5CKI

(1)

— — — SCK1

(1)

SCL1

(1,3,4)

— — —

IOCC0 Y —

RC1 9 8 ANC1 — C1IN1-

C2IN1-

— — — — CCP4

(1)

——SDI1

(1)

SDA1

(1,3,4)

— CLCIN2

(1)

— IOCC1 Y —

RC2 8 7 ANC2 — C1IN2-

C2IN2-

— — MDCIN1

(1)

— — — — — — — —

IOCC2 Y —

RC3 7 6 ANC3 — C1IN3-

C2IN3-

——MDMIN

(1)

T5G

(1)

CCP2

(1)

——SS1

(1)

— CLCIN0

(1)

— IOCC3 Y —

RC4 6 5

ANC4 — — — — —

T3G

(1)

— — — SCK2

(1)

SCL2

(1,3,4)

(1)

CLCIN1

(1)

— IOCC4 Y —

RC5 5 4 ANC5 — — — — MDCIN2

(1)

T3CKI

(1)

CCP1

(1)

——SDI2

(1)

SDA2

(1,3,4)

(1)

(1,3

)

——IOCC5 Y —

VDD 1 16

— — — — — — — — — — — — — — — —

VDD

VSS 14 13 — — — — — — — — — — — — — — — — VSS

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: These pins are configured for I

C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

PIC16LF18324-I/ST

Mfr. #:

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Manufacturer:

Microchip Technology

Description:

8-bit Microcontrollers - MCU 8-BIT MCU, 7KB Flash 512 RAM, 256 EEPROM

Lifecycle:

New from this manufacturer.

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PIC16LF18324-I/ST

PIC16LF18324-I/ST

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