ISL84525IUZ-T

10
FN6042.3
February 24, 2012
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and V+ or GND.
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. TURN - ON TIME vs SUPPLY VOLTAGE FIGURE 12. TURN - OFF TIME vs SUPPLY VOLTAGE
R
ON
(Ω)
V+ (V)
345678910111213
V
COM
= (V+) - 1V
I
COM
= 1mA
0
100
200
50
150
250
-40°C
+85°C
+25°C
R
ON
(Ω)
V
COM
(V)
0 4 6 8 10 12
2
V+ = 3.3V
I
COM
= 1mA
30
40
50
60
70
80
+85°C
-40°C
+25°C
V+ = 12V
60
80
100
120
140
+25°C
-40°C
+85°C
V+ = 5V
75
100
150
200
225
175
125
+25°C
-40°C
+85°C
V+ (V)
23456789101112
V
COM
= (V+) - 1V
t
ON
(ns)
50
100
150
200
250
300
350
0
-40°C
+85°C
+25°C
t
OFF
(ns)
V+ (V)
23456789101112
V
COM
= (V+) - 1V
10
20
30
40
50
60
70
80
90
100
110
120
+85°C
-40°C
+25°C
ISL84524, ISL84525
11
FN6042.3
February 24, 2012
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL84524: 193
ISL84525: 193
PROCESS:
Si Gate CMOS
FIGURE 13. FREQUENCY RESPONSE FIGURE 14. CROSSTALK AND OFF ISOLATION
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
FREQUENCY (MHz)
+3
0
-3
NORMALIZED GAIN (dB)
GAIN
PHASE
V+ = 5V
0
45
90
135
180
PHASE (DEGREES)
1 10 100 600
R
L
= 50
V
IN
= 5V
P-P
V
IN
= 0.2V
P-P
V
IN
= 5V
P-P
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
V+ = 3V to 12V
Q (pC)
V
COM
(V)
012345
-0.50
0
0.50
1.00
0.75
0.25
-0.25
V+ = 3.3V
V+ = 5V
ISL84524, ISL84525
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6042.3
February 24, 2012
ISL84524, ISL84525
Mini Small Outline Plastic Packages (MSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums and to be determined at Datum plane
.
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
L
0.25
(0.010)
L1
R1
R
4X θ
4X θ
GAUGE
PLANE
SEATING
PLANE
EE1
N
12
TOP VIEW
INDEX
AREA
-C-
-B-
0.20 (0.008) A
B
C
SEATING
PLANE
0.20 (0.008) C
0.10 (0.004) C
-A-
-H-
SIDE VIEW
b
e
D
A
A1
A2
-B-
END VIEW
0.20 (0.008) C
D
E
1
C
L
C
a
- H -
-A -
- B -
- H -
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.037 0.043 0.94 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.030 0.037 0.75 0.95 -
b 0.007 0.011 0.18 0.27 9
c 0.004 0.008 0.09 0.20 -
D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4
e 0.020 BSC 0.50 BSC -
E 0.187 0.199 4.75 5.05 -
L 0.016 0.028 0.40 0.70 6
L1 0.037 REF 0.95 REF -
N10 107
R 0.003 - 0.07 - -
R1 0.003 - 0.07 - -
5
o
15
o
5
o
15
o
-
α
0
o
6
o
0
o
6
o
-
Rev. 0 12/02
θ

ISL84525IUZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SWITCH DPDT 5V 150OHM 10MSOP IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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