CAT24C208WI-GT3

© Semiconductor Components Industries, LLC, 2009
May, 2018 Rev. 7
1 Publication Order Number:
CAT24C208/D
CAT24C208
EEPROM Serial 8-Kb I
2
C
Dual Port
Description
The CAT24C208 is an EEPROM Serial 8Kb I
2
C Dual Port
internally organized as 4 segments of 256 bytes each. The
CAT24C208 features a 16byte page write buffer and can be accessed
from either of two separate I
2
C compatible ports, DSP (SDA, SCL)
and DDC (SDA, SCL).
Arbitration between the two interface ports is automatic and allows
the appearance of individual access to the memory from each
interface.
Features
Supports Standard and Fast I
2
C Protocol
2.5 V to 5.5 V Operation
16Byte Page Write Buffer
Schmitt Triggers and Noise Protection Filters on I
2
C Bus Input
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
SOIC 8lead Package
This Device is PbFree, Halogen Free/BFR Free, and RoHS
Compliant
Figure 1. Block Diagram
ARBITRATION
LOGIC
DISPLAY
CONFIGURATION
REGISTER
D
ARRAY
EDID SEL
V
SS
DSP SCL
DSP SDA
CONTROL
LOGIC
DSP V
CC
DDC V
CC
E
C
O
D
E
R
S
D
E
C
O
D
E
R
S
DDC
CONTROL
LOGIC
MEMORY
1K X 8
DDC SCL
DDC SDA
www.onsemi.com
PIN CONFIGURATION
DDC SDA
EDID SEL
DDC V
CC
V
SS
DSP SDA
DSP SCL
DSP V
CC
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
SOIC8
W SUFFIX
CASE 751BD
DDC SCL
SOIC (W)
(Top View)
CAT24C208
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2
Table 1. PIN DESCRIPTION
Pin Number Pin Name Function
1 DSP V
CC
Device power from display controller
2 DSP SCL The CAT24C208 DSP serial clock bidirectional pin is used to clock all data transfers into or out of the
device DSP SDA pin and is also used to block DSP Port access when DDC Port is active.
3 DSP SDA DSP Serial Data/Address. The bidirectional DSP serial data/address pin is used to transfer data into
and out of the device from a display controller. The DSP SDA pin is an open drain output and can be
wireOR’ed with other open drain or open collector outputs.
4 V
SS
Device ground.
5 DDC SDA DDC Serial Data/Address. The bidirectional DDC serial data/address pin is used to transfer data into
and out of the device from a DDC host. The DDC SDA pin is an open drain output and can be wire
OR’ed with other open drain or open collector outputs.
6 DDC SCL The CAT24C208 DDC serial clock bidirectional pin is used to clock all data transfers into or out of the
device DDC SDA pin, and is used to block DDC Port for access when DSP Port is active.
7 EDID SEL EDID select. The CAT24C208 EDID select input selects the active bank of memory to be accessed
via the DDC SDA/SCL interface as set in the configuration register.
8 DDC V
CC
Device power when powered from a DDC host.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias –55 to +125 °C
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) –2.0 to +V
CC
+2.0 V
V
CC
with Respect to Ground –2.0 to +7.0 V
Package Power Dissipation Capability (T
A
= 25°C) 1.0 W
Lead Soldering Temperature (10 secs) 300 °C
Output Short Circuit Current (Note 2) 100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 3. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Units
N
END
(Note 3) Endurance MILSTD883, Test Method 1033 1,000,000 Cycles/Byte
T
DR
(Note 3) Data Retention MILSTD883, Test Method 1008 100 Years
V
ZAP
(Note 3) ESD Susceptibility JEDEC Standard JESD 22 2000 Volts
I
LTH
(Notes 3 and 4) Latchup JEDEC Standard 17 100 mA
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latchup protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
Table 4. CAPACITANCE (T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol Parameter Conditions Min Typ Max Units
C
I/O
(Note 5) Input/Output Capacitance (Either DSP or DDC SDA) V
I/O
= 0 V 8 pF
C
IN
(Note 5) Input Capacitance (EDID, Either DSP or DDC SCL) V
IN
= 0 V 6 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
CAT24C208
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3
Table 5. D.C. OPERATING CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter Test Conditions Min Typ Max Units
I
CC
Power Supply Current f
SCL
= 100 KHz 3 mA
I
SB
Standby Current (V
CC
= 5.0 V) V
IN
= GND or either DSP or DDC V
CC
50
mA
I
LI
Input Leakage Current V
IN
= GND to either DSP or DDC V
CC
10
mA
I
LO
Output Leakage Current V
OUT
= GND to either DSP or DDC V
CC
10
mA
V
IL
Input Low Voltage 1 V
CC
x 0.3 V
V
IH
Input High Voltage V
CC
x 0.7 V
CC
+ 0.5 V
VHYS Input Hysteresis 0.05 V
V
OL1
Output Low Voltage (V
CC
= 3 V) I
OL
= 3 mA 0.4 V
V
CCL1
Leakage DSP V
CC
to DDC V
CC
±100
mA
V
CCL2
Leakage DDC V
CC
to DSP V
CC
±100
mA
Table 6. A.C. CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, unless otherwise specified.)
Symbol Parameter Min Max Units
READ & WRITE CYCLE LIMITS
F
SCL
Clock Frequency 400 kHz
T
I
(Note 6) Noise Suppression Time Constant at SCL, SDA Inputs 100 ns
t
AA
SCL Low to SDA Data Out and ACK Out 0.9
ms
t
BUF
(Note 6) Time the Bus Must be Free Before a New Transmission Can Start 1.3
ms
t
HD:STA
Start Condition Hold Time 0.6
ms
t
LOW
Clock Low Period 1.3
ms
t
HIGH
Clock High Period 0.6
ms
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition) 0.6
ms
t
HD:DAT
Data In Hold Time 0 ns
t
SU:DAT
Data In Setup Time 100 ns
t
R
(Note 6) SDA and SCL Rise Time 300 ns
t
F
(Note 6) SDA and SCL Fall Time 300 ns
t
SU:STO
Stop Condition Setup Time 0.6
ms
t
DH
Data Out Hold Time 100 ns
Table 7. POWERUP TIMING (Notes 6 and 7)
Symbol Parameter Min Typ Max Units
t
PUR
Powerup to Read Operation 1 ms
t
PUW
Powerup to Write Operation 1 ms
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol Parameter Min Typ Max Units
t
WR
Write Cycle Time 5 ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.

CAT24C208WI-GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 8K-Bit Dual Port
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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