CAT24C208WI-GT3

CAT24C208
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7
DSP Interface
The DSP interface is similar to I
2
C bus serial interface.
Without the segment pointer, the maximum accessible
memory space is 256 bytes of segment 00h only. In the
sequential mode the wrap around will be in the same
segment also. Figures 14 to 17 show the read and write on
the DSP Port.
Figure 14. Random Access Read
START 1010 0000 ACK A7 A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP
Figure 15. Sequential Read
START 1010 0000 ACK A7 A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP
Figure 16. Byte Write
START 1010 0000 ACK A7 A0 ADDRESS ACK ACKDATA STOP
Figure 17. Page Write
START 1010 0000 ACK A7 A0 ADDRESS ACK DATA0 ACK ......... DATA15 ACK STOP
The segment pointer is used to expand the available DSP
port addressable memory to 1 k bytes, divided into four
segments of 256 bytes each. The four segments are selected
by two bits S
1
S
0
= 00, 01, 10, 11 in the segment address.
Figures 18 to 21 show the random read, sequential read, byte
write and page write.
Figure 18. Random Access Read
START 1010 0000 ACK A7 A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP
START 0110 0000 ACK ACK
xxxx xxS
1
S
0
Segment ADDRESS
Figure 19. Sequential Read
START 1010 0000 ACK A7 A0 ADDRESS ACK START 1010 0001 ACK DATA0 ACK ......... DATAN NOACK STOP
START 0110 0000 ACK ACK
xxxx xxS
1
S
0
Segment ADDRESS
Figure 20. Byte Write
START 1010 0000 ACK A7 A0 ADDRESS ACK DATA ACK STOP
START 0110 0000 ACK ACK
xxxx xxS
1
S
0
Segment ADDRESS
Figure 21. Page Write
START 1010 0000 ACK A7 A0 ADDRESS ACK DATA0 ACK ......... DATA15 ACK STOP
START 0110 0000 ACK ACK
xxxx xxS
1
S
0
Segment ADDRESS
CAT24C208
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8
Arbitration
The device performs a simplistic arbitration between the
DDC and DSP ports. While the arbitration scheme described
is not foolproof, it does prevent most errors.
Arbitration logic within the device monitors activity on
DDC_SCL and DSP_SCL. When both I
2
C ports are idle,
DDC_SCL and DSP_SCL are both high and the arbitration
logic is inactive. When a START condition is detected on
either port, the opposite port SCL line is pulled low, holding
off activity on that port. When the initiating SCL line has
remained high for one full second, the arbitration logic
assumes that the initiating devices is finished and releases
the other SCL line. If the noninitiating device has been
waiting for access, it can now read or write the device.
Table 9. CONFIGURATION REGISTER
Register Function
MSB LSB
7 6 5 4 3 2 1 0
Configuration Register X X X X WE AB1 AB0 NB
Function Description
NB: Number of memory banks in DDC port memory map. 0 = 2 Banks, 1 = 1 Bank
AB0: Active Bank Control Bit 0 (See Table 10)
AB1: Active Bank Control Bit 1 (See Table 10)
WE DDC: Write Enable 0 = Write Disabled, 1= Write Enabled (Note 8)
8. WE affects only write operations from the DDC port, not the display port. The display port always has write access.
Table 10. CONFIGURATION REGISTER TRUTH TABLE
AB1 AB0 NB EDID Select Pin Active Bank
0 X 0 0 Lower Bank
0 X 0 1 Upper Bank
1 0 0 X Lower Bank
1 1 0 X Upper Bank
X X 1 X Lower (only) Bank
The configuration register is a nonvolatile register and is available from either DSP or DDC port at address 62h / 63h for
write and read resp.
Table 11. READ CONFIGURATION REGISTER
START 0110 0011 ACK DATA NO ACK STOP
Table 12. WRITE CONFIGURATION REGISTER
START 0110 0010 ACK DUMMY ADDRESS ACK XXXX WE AB1 AB0 NB ACK STOP
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
Package
Type
Temperature Range
Lead
Finish
Shipping
CAT24C208WIGT3 24C208WI SOIC8 Industrial NiPdAu Tape & Reel, 3,000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
9. All packages are RoHScompliant (Leadfree, Halogenfree).
10.The standard lead finish is NiPdAu.
11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by the Philips Corporation to carry the I
2
C bus protocol.
SOIC 8, 150 mils
CASE 751BD01
ISSUE O
DATE 19 DEC 2008
E1 E
A
A1
h
θ
L
c
e
b
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L
0.40 1.27
1.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34272E
ON SEMICONDUCTOR STANDARD
SOIC 8, 150 MILS
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2

CAT24C208WI-GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 8K-Bit Dual Port
Lifecycle:
New from this manufacturer.
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