MAX5922
+48V, Single-Port Network Power Switch
For Power-Over-LAN
10 ______________________________________________________________________________________
PIN NAME FUNCTION
*AGND
Analog Ground. This is the return of analog power input. AGND can vary ±4V from DGND. AGND and
DGND must be connected together at a single point in the system.
1, 2 DRAIN
Drain connection for the integrated MOSFET. Connect a sense resistor, R
SENSE
, from DRAIN to IN.
These pins are also the current-sense resistor negative terminal. R
SENSE
sets the overcurrent-limit
and open-circuit detection threshold. These two pins must be connected together.
3, 6, 26 N.C.
No Connection. Not internally connected. Leave pins 6 and 26 open. Pins 6 and 26 are left
unconnected to provide additional spacing between the high-voltage pins and other pins.
4IN
Input Voltage. Connect to a positive voltage source between +32V to +60V from IN to AGND. This is
the current-sense resistor positive terminal. Bypass to AGND with a 47µF, 100V electrolytic capacitor
and a 0.1µF, 100V ceramic capacitor. Place the ceramic capacitor close to this pin.
5 RCL
Classification Sense Resistor. Connect a 150 ±1% resistor from RCL to IN for sensing the
classification current. Leave RCL floating when the PD classification function is not used.
7 AGND_S
Analog Ground Sense. Connect a 1 resistor from AGND_S to AGND. This resistor protects the IC
during an output short-circuit condition.
8 UVLO
Undervoltage Lockout Adjustment Input. Referenced to AGND. Connect to the center point of a
resistive-divider from IN to AGND to adjust the UVLO threshold. Leave open for default value.
9 RDT
Detection Sense Resistor. Connect an 18.2k ±1% resistor from RDT to AGND for sensing the PD
detection current. Add a 680nF capacitor in parallel to this resistor to filter out the power-line noise.
Connect RDT to AGND when the PD detection function is not used.
10 FAULT
Fault Signal Open-Drain Logic Output. Reference to DGND. FAULT is latched low when:
1. An overtemperature condition occurs and/or,
2. An overcurrent condition that has lasted for more than t
OC
.
11 POK
Power-OK, Open-Drain Logic Output. Reference to DGND. POK goes open drain a time t
POK_HIGH
after V
OUT
raises to within V
THPOK
from V
IN
. POK goes low a time t
POK_LOW
after V
OUT
falls out of the
V
THPOK
from V
IN
.
12 ZC
Zero-Current Fault Signal. Open-drain logic output. Reference to DGND. ZC is latched low when there
is a zero-current condition lasting longer than t
ZCDEL
. ZC is open-drain otherwise. The zero-current
detection circuit is enabled immediately after the POK signal goes high. The ZC is unlatched after a
valid PD has been detected and eventually classified.
13 TP1 Must be Left Open or Connected to AGND
14 TP2 Must be Left Open or Connected to AGND
15 TP3 Must be Left Open or Connected to AGND
16 CL2 Classification Report Logic Output Bit 2. See the PD Classification section (Table 2).
17 CL1 Classification Report Logic Output Bit 1. See the PD Classification section (Table 2).
18 CL0 Classification Report Logic Output Bit 0. See the PD Classification section (Table 2).
19 DGND
Digital Ground. DGND can vary ±4V from AGND. DGND and AGND must to be connected together at
a single point in the system.
20 LATCH
Fault Management Selection Digital Input. Referenced to DGND. Connect to a logic high to latch off
after a fault condition. Connect to a logic low for automatic restart after a fault condition (see the Fault
Management section).
Pin Description
*This is not a device pin.
MAX5922
+48V, Single-Port Network Power Switch
For Power-Over-LAN
______________________________________________________________________________________ 11
PIN NAME FUNCTION
21 ZC_EN
Zero-Current-Detection Enable Logic Input. Referenced to DGND. Connect ZC_EN to a logic high to
enable the zero-current detection circuitry. Connect ZC_EN to a logic low to disable this function.
22 EN
ON/OFF Control-Logic Input. Referenced to DGND. Connect to a logic high to enable the device.
Connect to a logic low to disable the device and reset a latched-off condition.
23 V
DIG
Digital Supply Voltage. V
DIG
is the supply voltage for the internal digital logic circuity. EN, LATCH,
CLASS, DET_DIS, DCA, and ZC_EN input logic thresholds are automatically scaled to the voltage on
V
DIG
. See the Typical Application Circuit for proper filtering.
24 CLASS
Classification Enable Digital Input. Connect to DGND to disable the classification function. Connect to
V
DIG
to enable the classification function.
DET_DIS
PD Detection Disable Logic Input. When DET_DIS is connected to a logic high, the part skips the
detection and classification (regardless of the status of CLASS) phases and powers on immediately
after EN = high (MAX5922B/MAX5922C only).
25
DCA
Detection Collision Avoidance Logic Input. Connect to a logic high to activate the detection collision
avoidance circuitry for midspan system. Connect to DGND to disable this function. (MAX5922A only).
See the Detection Collision Avoidance section.
27, 28 OUT Output Voltage
Pin Description (continued)
CLASS
POK
VDIG
EN
LATCH
ZC_EN
DCA
CL2
CL1
CL0
DGND
N
N
N
N
N
N
ZC
FAULT
LOGIC-
LEVEL
TRANSLATOR
LOGIC
CONTROL
ANALOG
CONTROL
VOLTAGE
REGULATOR
OSC
DETECTION
AND
CLASSIFICATION
CIRCUITRY
CHARGE
PUMP
N
IN
CSP
DRAIN
OUT
UVLO
RCL
RDT
AGND
MAX5922
Figure 1. MAX5922 Block Diagram
MAX5922
+48V, Single-Port Network Power Switch
For Power-Over-LAN
12 ______________________________________________________________________________________
Detailed Description
The MAX5922 is a single-port network power controller
with an integrated power MOSFET, operating from a
+32V to +60V supply rail. The device is specifically
designed for PSE in power-over-LAN applications and is
fully compliant to the IEEE 802.3af standard. The
MAX5922 provides PD discovery, classification, current
limit, and other necessary functions for an IEEE 802.3af-
compliant PSE.
The MAX5922 operates in three different modes: PD
detection mode, PD classification mode, and power
mode. Figures 2 and 4 illustrates the devices functional
operation.
PD Detection Mode
Once powered up and enabled, the MAX5922 probes
the output for a valid PD. A valid PD should have a 25k
discovery signature characteristic as specified in the
IEEE 802.3af standard. Table 1 shows the IEEE 802.3af
specification for a PSE detection of PDs (see the Typical
Application Circuit and Figure 3 (MAX5922 startup
sequence)).
The MAX5922 performs the PD detection by forcing a
probe voltage (V
PBI
= 4V) at the OUT pin and senses the
current out of this pin. The sensed current is sampled and
held t
DET
(88ms) after the probing voltage is sent. The
probe voltage is then switched to V
PBII
= 8V. At the end
of another t
DET
period, the ratio of the difference of the
two test voltages and sensed currents (V/I) is calculat-
ed to determine the PD resistance. The MAX5922 PD
detection circuitry checks for a valid PD resistive signa-
ture between 19k and 26.5k, with a parallel capaci-
tance of up to 0.6µF. The MAX5922 PD detection circuit
rejects all PDs showing resistive signature of less than
15k or greater than 33k, and/or a capacitive signature
greater than 6µF. Any resistive signature between 15k
to 19k, or between 26.5k to 33k, and/or a capaci-
tance between 0.6µF to 6µF can produce unpredictable
detection results. If the MAX5922 does not detect a valid
PD signature, it continually sends the probe voltages to
the output indefinitely (see Figure 5).
The detection current reference is set by an external
resistor (R
RDT)
) connected from the RDT pin to AGND.
This resistor should be an 18.2k ±1%, with an optional
680nF capacitor in parallel for filtering out power-line
noise. An internal diode in series with the detection volt-
age source and OUT is provided to restrict PD detec-
tion to the 1st quadrant as specified by the IEEE
standard 802.3af (see Figure 3). To prevent damage to
non-PD devices and to protect itself from output short
circuit, the MAX5922 limits the current out of the OUT
pin during PD detection to 1.5mA (max).
For midspan systems where power is delivered to the
PD through the spare pairs, the detection collision
avoidance must be activated. In this mode, after every
failed PD detection cycle, the MAX5922A/MAX5922C
enter a back-off mode where they drive the OUT pin
into high impedance for t
DCA
(2.8s). The DCA pin must
be connected high (MAX5922A) to activate the detec-
tion collision avoidance circuitry (if connected low, the
detection collision avoidance circuitry is disabled). The
MAX5922C has the detection collision avoidance cir-
cuitry permanently enabled (see the Typical
Application Circuit). After t
DCA
, the MAX5922A (with
DCA high) and the MAX5922C resume PD detection
operation. The MAX5922B has the detection collision
avoidance circuitry permanently disabled.
Detection Enable/Disable
The MAX5922A has the PD detection mode permanently
enabled. The MAX5922B/MAX5922C are equipped with
a DET_DIS pin, which provides the option of enabling or
disabling the power-device detection phase. With the
DET_DIS pin connected high, the PD detection and clas-
sification phases are disabled regardless of the status of
the class pin. With the DET_DIS pin connected low, the
PD detection is enabled.
Table 1. IEEE802.3af PD Specification
PARAMETER
VALID
PD DETECTION
SIGNATURE
NON-VALID
PD DETECTION
SIGNATURE
V/I (Slope)
19k < R
PD
<
26.5k
15k > R
PD
or
R
RD
> 33k
Input Capacitance C
PD
< 0.6µF C
PD
> 6µF
Offset Voltage Up to 2.0V
Current Offset Up to 12µA

MAX5922AEUI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Hot Swap Voltage Controllers 48V Single-Port Network Power Switch
Lifecycle:
New from this manufacturer.
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