Video Clock Synthesizer with I
2
C Programmable Delay
MDS ICS1523 ZC 13 Revision 020811
Integrated Device Technology, Inc.Tech Support: www.idt.com/go/clockhelp
ICS1523
11.2 Programming Flow for Modifying PLL and DPA Settings
BEGIN
Determine Horizontal Total
HTOTAL
Program Input Control Register Reg0x0
Typically = 41h
(Coast disabled, Positive edge of HSYNC, Internal Feedback,
FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin
Program DPA Reg0x5
DPA Resolution 0x5 = (Value From Note 8 Table)
DPA Offset, 0x4:5~0 = 0
Full S/W Reset
Reg0xA = 5Ah
Correct Phase
Relationship?
Decrement Charge
Pump Current
Reg0x1:2~0
END
Program Feedback Divider Reg0x2, Reg0x3
Internal Feedback Divider (0x3 & 0x2) = HTOTAL - 8
Program Loop Control Register Reg0x1
VCO Divider 0x1:5~4 = (Maximum value where
Required Output Frequency * VCOD < 500 MHz)
Typical Charge Pump Current 0x1:2~0= 011b
Program Output Control Reg0x6
Enable the desired outputs
Program OSC Divider Reg0x7
Select Desired Input Reg0x7:7
Select OSC divider value (if needed)
Increment DPA
Offset
Reg0x4
Program Internal Filter Reg0x4
Select Internal Filter 0x4:7 = 1
Yes
Yes
No
PLL LOCKED?
LOCK Pin or
Read 0x12:1
No
Video Clock Synthesizer with I
2
C Programmable Delay
ICS1523
MDS ICS1523 ZC 14 Revision 020811
Integrated Device Technology, Inc.Tech Support: www.idt.com/go/clockhelp
Section 12 Timing Diagrams
Figure 12-1 DPA Operation
DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]
(# of DPA Elements Available)[0x5:1-0]
Table 12-1 DPA Offset Ranges
Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass
the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after
a DPA Software reset (0x8=xA)
Register 5
0x4:5-0
Maximum
DPA Clock Range in MHz
1~0
Total # of DPA
Elements
Selected #
of DPA
Elements
Min Max
00 16
0F
48 160
01 32
1F
24 80
11 64
3F
12 40
HSYNC
DPA Offset when
DPA_OS [5-0] = 0
.
.
.
One full speed clock period
DPA Offset when
DPA_OS [5-0] = 1
DPA Offset when
DPA_OS [5-0] = 2
DPA Offset when
DPA_OS [5-0] = Max
1 unit of DPA delay
2 units of DPA delay
Maximum units of DPA delay
Fixed delay See Figure 12-2 and Figure 12-3
1 unit of DPA delay
Video Clock Synthesizer with I
2
C Programmable Delay
MDS ICS1523 ZC 15 Revision 020811
Integrated Device Technology, Inc.Tech Support: www.idt.com/go/clockhelp
ICS1523
12.1 Timing for 0x0:2=0
Figure 12-2 0x0:2=0 Timing Diagram
Table 12-2 0x0:2=0 Timing Values
Symbol Parameter Minimum Typical Maximum Units
T2 HSYNC High to FUNC High
(DPA Offset = 0)
T8 + T3 ns
T3 HSYNC High to PECL CLK+ High
(DPA Offset = 0)
-7 -ns
T4 PECL Clock Low to SSTL_3 Clock Low
Delay
00.20.6ns
T5 PECL Clock Low to FUNC High Delay 0.6 1.0 1.6 ns
T6 PECL Clock Low to PECL/2 High Clock 0.6 1.0 1.6 ns
T7 PECL Clock Low to SSTL_3 CLK/2 Delay 0.4 0.9 1.2 ns
T8 PECL Clock High Time - 0.5 - UI

ICS1523MT

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IC VIDEO CLK SYNTHESIZER 24-SOIC
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