MAX8702/MAX8703
Dual-Phase MOSFET Drivers
with Temperature Sensor
6 _______________________________________________________________________________________
Pin Description
MAX8703
PWM1
Phase 1 PWM Logic Input. DH1 is high when PWM1 is high; DL1 is high when PWM1 is low.
2 2
PWM2
Phase 2 PWM Logic Input. DH2 is high when PWM2 is high; DL2 is high when PWM2 is low.
3 3
AGND
Analog Ground. The AGND and PGND_ pins must be connected externally at one point close to
the IC. Connect the device’s exposed backside pad to AGND.
4 —
TSET
Temperature-Set Input. Connect an external 1% resistor from TSET to AGND to set the trip point.
R
TSET
= 85,210 / T - 745,200 / T
2
- 195, where R
TSET
is the temperature-setting resistor in kΩ
and T is the trip temperature in Kelvin.
5 —
DRHOT
Driver-Hot-Indicator Output. DRHOT is an open-drain output. Pull up with an external resistor.
When the device’s temperature exceeds the programmed set point, DRHOT is pulled low.
6 — I.C. Internally Connected. Connect to AGND.
7 7 V
CC
Internal Control Circuitry Supply Input. The input voltage range is from 4.5V to 5.5V. Bypass V
CC
to AGND with a 1µF ceramic capacitor. The maximum resistance between V
CC
and V
DD
should
be 10Ω.
8 8
BST2
Phase 2 Bootstrap Flying-Capacitor Connection. An optional resistor in series with BST2 allows
the DH2 pullup current to be adjusted.
9 9
DH2
Phase 2 High-Side Gate-Driver Output. DH2 swings between LX2 and BST2.
10 10 LX2
Phase 2 Inductor Switching Node Connection. LX2 is the internal lower supply rail for the DH2
high-side gate driver. LX2 is also the input to the skip-mode zero-crossing comparator.
11 11
PGND2
Phase 2 Power Ground. PGND2 is the internal lower supply rail for the DL2 low-side gate driver.
12 12 DL2
Phase 2 Low-Side Gate-Driver Output. DL2 swings between PGND2 and V
DD
. DL2 is high in
shutdown.
13 13 V
DD
DL_ Gate-Driver Supply Input. The input voltage range is from 4.5V to 5.5V. Bypass V
DD
to the
power ground with a 2.2µF ceramic capacitor.
14 14 DL1
Phase 1 Low-Side Gate-Driver Output. DL1 swings between PGND1 and V
DD
. DL1 is high in
shutdown.
15 15
PGND1
Phase 1 Power Ground. PGND1 is the internal lower supply rail for the DL1 low-side gate driver.
16 16 LX1
Phase 1 Inductor Switching Node Connection. LX1 is the internal lower supply rail for the DH1
high-side gate driver. LX1 is also the input to the skip-mode zero-crossing comparator.
17 17
DH1
Phase 1 High-Side Gate-Driver Output. DH1 swings between LX1 and BST1.
18 18
BST1
Phase 1 Bootstrap Flying-Capacitor Connection. An optional resistor in series with BST1 allows
the DH1 pullup current to be adjusted.
19 19
SKIP
Pulse-Skipping-Mode Control Input. The pulse-skipping mode is enabled when SKIP is low.
When SKIP is high, both drivers operate in PWM mode (i.e., except during dead times, DL_ is the
complement of DH_).
20 20
SHDN
S hutd ow n C ontr ol Inp ut. W hen S HD N and S KIP ar e l ow , D H _ i s for ced l ow , D L_ for ced hi g h, and
the d evi ce enter s i nto a l ow - p ow er shutd ow n state. Tem p er atur e sensi ng i s d i sab l ed i n shutd ow n.
— 4, 5, 6
N. C.
No Connection. Not internally connected.
