Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-20 ns -25 ns -35 ns -45ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
twc WriteCycleTime 20 — 25 — 35 — 45 — ns
tsce CEtoWriteEnd 12 — 18 — 25 — 35 — ns
tAw AddressSetupTime 12 — 15 — 25 — 35 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tsA AddressSetupTime 0 — 0 — 0 — 0 — ns
tPwb LB, UBValidtoEndofWrite 12 — 18 — 30 — 35 — ns
tPwe1 WE Pulse Width (OE=HIGH) 12 — 18 — 30 — 35 — ns
tPwe2 WE Pulse Width (OE=LOW) 17 — 20 — 30 — 35 — ns
tsd DataSetuptoWriteEnd 9 — 12 — 15 — 20 — ns
tHd Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHzwe
(3)
WELOWtoHigh-ZOutput — 9 — 12 — 20 — 20 ns
tLzwe
(3)
WEHIGHtoLow-ZOutput 3 — 5 — 5 — 5 — ns
Notes:
1. TestconditionsforIS61WV6416LLassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulse
levels of 0.4V to Vdd-0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtothe
rising or falling edge of the signal that terminates the write.