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MR45V256AMAZAAT-L

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
PEDR45V256A-05
MR45V256A
4/20
SPI mode0（CPOL=0, CPHA=0）
SPI mode3（CPOL=1, CPHA=1）
Status Register
Status Register data are volatile.
Set Status Register data by WRSR(Write status register) command, after power on.
Name Function
WIP Fixed to 0.
WEL Write Enable Latch. This indicates internal WEL condition.
BP0,BP1 Block Protect :These bits can be changed protect area .
This is the software protect.
SRWD
Status Register Write Disable（ SRWD ） : SRWD controls the effect of the
hardware WP# pin. This device will be in hardware-protect by combination of
SRWD and WP#.
0 Fixed to 0.
SRWD 0 0 0 BP1 BP0 WEL WIP
b7 b0
Status Register Write Disable
Block Protect Bits
Write Enable Latch
Write In Progress (Always 0)
CS
#
SC
K
SI LSBMSB
CS
#
SC
K
SI LSB MSB
PEDR45V256A-05
MR45V256A
5/20
Operation-Code
Operation codes are listed in the table below.If the device receives invalid operation code,the device will be
diselected.
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
PEDR45V256A-05
MR45V256A
6/20
Commands
WREN(Write Enable)
It is necessary to set Write Enable Latch（WEL）bit before write-operation (WRITE and WRSR).
WREN command sets WEL bit.
WRDI(Write Disable)
WRDI command resets WEL bit.
CS
#
SC
K
SI
WP
#
Fixed “H”
01 23456 7
SO
High-Z
CS
#
SC
K
SI
WP
#
Fixed “H”
0 1 2 3 4 5 6 7
SO
High-Z
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MR45V256AMAZAAT-L

Mfr. #:
Buy MR45V256AMAZAAT-L
Manufacturer:
Description:
F-RAM 256K; SPI; 3.3V FeRAM 15MHz
Lifecycle:
New from this manufacturer.
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