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MR45V256AMAZAAT-L

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
PEDR45V256A-05
MR45V256A
7/20
RDSR(READ Status Register)
The RDSR command allows to read data of status register.
WRSR(WRITE Status Register）
WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable
Latch（WEL）bit by WREN command before executing WRSR.
CS
#
SC
K
SI
WP
#
Fixed “H”
0
SO
High-Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SRWD BP1 BP0 WEL WIP SRWD000
76543 2 1 07
CS
#
SC
K
SI
0
SO
High-Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BP0 X X
76543 2 1 0
BP1 XXXSRWD
Note:
WP#=Fix ”H”
PEDR45V256A-05
MR45V256A
8/20
READ(Read from Memory Array)
READ command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial
input”SI”. The inputted adresses are loaded to internal register,then the data from corresponded address is
output at serial-output “SO”.If CS# will keep “L”,the internal adress will be incresed automatically after 8 clocks
and will output the data from new-address.When it reaches the most significant adress,the adress counter rolls
over tostarting adress,and reading cycle can be continued infinitely.
CS
#
SC
K
SI
0
SO
High-Z
1 2 3 4 5 6 7 8 9 10 11 20 21 22 23
A2 A1 A0
15 14 13 3 2 1 0
A3 A13A14X
16bit Address An
12
A12
CS
#
SC
K
SI
24
SO
25 26 27 28 29 30 31 32 33 34 35 38 39 m
Data Out (An)
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Data Out (An+1)
Qx
36 37
Note : WP# = fixed ”H”
PEDR45V256A-05
MR45V256A
9/20
WRITE(Write to Memory Array）
Write command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial
input”SI”. Writing is terminated when CS# goes high after data-input. If CS# will keep “L”,the internal adress
will be incresed automatically.When it reaches the most significant adress,the adress counter rolls over to
starting adress 0000h,and writing cycle(overwriting) can be continued infinitely.
WRITE(1Byte)
WRITE(Page)
CS
#
SC
K
SI
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23
A2 A1 A0
15 14 13 3 2 1 0
A3 A13A14X
16bit Address An
12
A12
CS
#
SC
K
SI
Note : WP# = Fixed ”H” , SO=High-Z
24 25 26 27 28 29 30 31
Data Byte 1
D7 D6 D5 D4 D3 D2 D1 D0
CS
#
SC
K
SI
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23
A2 A1 A0
15 14 13 3 2 1 0
A3 A13A14X
16bit Address An
12
A12
CS
#
SC
K
SI
Note : WP# = Fixed ”H” , SO=High-Z
24 25 26 27 28 29 30 31 32 33 34 35 38 39
Data Byte 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte 2
36 37
CS
#
SC
K
SI
40 41 42 43 44 45 46 47
Data Byte 3
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte N
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MR45V256AMAZAAT-L

Mfr. #:
Buy MR45V256AMAZAAT-L
Manufacturer:
Description:
F-RAM 256K; SPI; 3.3V FeRAM 15MHz
Lifecycle:
New from this manufacturer.
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