AD5116 Data Sheet
Rev. B | Page 12 of 16
TEST CIRCUITS
Figure 32 to Figure 37 define the test conditions used in the Specifications section.
09657-030
A
W
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
Figure 32. Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
09657-031
A
W
B
DUT
V
MS
V+
V+ = V
DD
1LSB = V+/2
N
Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL)
09657-032
+
DUT
0
.1V
=
0.1V
I
WB
I
WB
W
B
NC = N
O CO
NNEC
T
R
W
A
NC
G
ND TO V
DD
Figure 34. Wiper Resistance
09657-033
A
W
B
V
M
S
~
V
A
V
D
D
V+
V+
=
V
DD
±
10%
ΔV
M
S
%
ΔV
DD
%
PSS
(
%
/
%
)
=
PS
RR
(
d
B
) = 20 log
ΔV
MS
ΔV
DD
Figure 35. Power Supply Sensitivity (PSS, PSRR)
09657-034
OFFSET
GND
A
B
DUT
W
+15V
V
IN
V
OUT
OP42
–15V
2.5V
Figure 36. Gain and Phase vs. Frequency
09657-035
DUT
I
C
M
W
B
V
D
D
G
ND
A
V
DD
GND
GND
V
DD
GND
V
DD
Figure 37. Common-Mode Leakage Current
Data Sheet AD5116
Rev. B | Page 13 of 16
THEORY OF OPERATION
The AD5116 digital programmable resistor is designed to
operate as a true variable resistor for analog signals within
the terminal voltage range of GND < V
TERM
< V
DD
. The resistor
wiper position is determined by the RDAC register contents.
The RDAC register is a standard logic register; there is no
restriction on the number of changes allowed.
The RDAC register can be programmed with any position
setting using the push button interface. Once a desirable wiper
position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-up. The storing of EEPROM
data takes approximately 20 ms; during this time, the device
is locked and does not accept any new operation, thus
preventing any changes from taking place.
The AD5116 is designed to support external push buttons
(tactile switches) directly, as shown in Figure 1.
RDAC REGISTER
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register
is 0x20, the wiper is connected to midscale of the variable
resistor. The RDAC register is controlled using the PD and PU
push buttons. The step-up and step-down operations require
the activation of the PU (push-up) and PD (push-down) pins.
These pins have 100 kΩ internal pull-up resistors that PU and
PD activate at logic high. The following paragraphs explain how
to increment the RDAC register, but all the descriptions are
valid to decrement the RDAC register, swapping PU by PD.
Manual Increment
The AD5116 features an adaptive debouncer that monitors the
duration of the logic high level of PU signal between bounces. If
the PU logic high level signal duration is shorter than 8 ms, the
debouncer ignores it as an invalid incrementing command.
Whenever the logic high level of PU signal lasts longer than
8 ms, the debouncer assumes that the last bounce is met and,
therefore, increments the RDAC register by one step. The wiper
is incremented by one tap position, as shown in Figure 2.
Auto Scan Increment
If the PU button is held for longer than 1 second, continuously
holding it activates auto scan mode, and the AD5116 increments
the RDAC register by one step every 140 ms until PU is
released. Typical timing is shown in Figure 3.
Low Wiper Resistance Feature
The AD5116 includes extra steps to achieve a minimum wiper
resistance. Between Terminal W and Terminal B, this extra step
is called bottom scale and the wiper resistance decreases from
70 Ω to 45 Ω. Between Terminal A and Terminal W, this extra
step is called top scale and connects the A and W terminals,
reducing the 1 LSB resistor typical at full-scale code. These new
extra steps are loaded automatically in the RDAC register after
zero-scale or full-scale position has been reached. The extra
steps are not equal to 1 LSB, and are not included in the INL,
DNL, R-INL, and R-DNL specifications.
Whenever the minimum R
WB
(= R
BS
) is reached, the resistance
stops decrementing. Any continuous holding of the PD to logic
high simply elevates the supply current. When R
AW
reaches the
minimum resistance (= R
TS
), continuous holding of PU only
elevates the supply current.
EEPROM
The AD5116 contains an EEPROM memory that allows
wiper position storage. Once a desirable wiper position is
found, this value can be saved into the EEPROM. Thereafter,
the wiper position will always be set at that position for any
future on-off-on power supply sequence.
AUTOMATIC SAVE ENABLE
At power-up, the AD5116 checks the level in the
ASE
pin. If the
pin is pulled low, as shown in Figure 38, the automatic store is
enabled. If the pin is pulled high, as shown in Figure 39,
automatic store is disabled and the RDAC register should be
stored manually. During the storage cycle, the device is locked
and does not accept any new operation preventing any changes
from taking place.
09657-036
AD5
1
16
100k
ASE
GND
Figure 38. Automatic Store Enables
Auto Save
If there is no activity on inputs during 1 second, the AD5116
stores the RDAC register data into EEPROM, as shown in
Figure 4.
Manual Store
The storage is controlled by the
ASE
pin, which is connected to
an adaptive debouncer. If the
ASE
pin is pulled low longer than
8 ms, the
AD5116 saves the RDAC register data into EEPROM,
as shown in Figure 5.
09657-037
AD5116
100k
ASE
V
DD
V
DD
Figure 39. Automatic Store Disables with Manual Storage
Push Button
AD5116 Data Sheet
Rev. B | Page 14 of 16
END SCALE RESISTANCE INDICATOR
When the auto save mode is enabled, the
ASE
pin also indicates
when the RDAC register reaches the maximum or minimum
scale. The AD5116 pulls the
ASE
pin high and holds it as long
as PD or PU is active, and the part is placed in the end scale
resistance (R
TS
or R
BS
), as shown in Figure 6. The typical pin
configuration is shown in Figure 40.
When the part is placed at the end of the resistance scale (R
TS
or
R
BS
), the
ASE
pin is pulled high during the debounce time, until
the RDAC register is incremented (R
BS
) or decremented (R
TS
) by
activating PU or PD.
09657-038
AD5116
100k
ASE
GND
Figure 40. Typical End Scale Indicator Circuit
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5116 employs a two-stage
segmentation approach as shown in Figure 41. The AD5116
wiper switch is designed with the transmission gate CMOS
topology and with the gate voltage derived from V
DD
.
09657-039
R
W
S
W
W
R
W
6-BIT
ADDRESS
DECODER
A
TS
BS
R
L
R
L
B
R
L
R
L
Figure 41. Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5116 includes a new feature to reduce the
resistance between terminals. These extra steps are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 70 Ω to 45 Ω. At top scale, the
resistance between Terminal A and Terminal W is decreased
by 1 LSB and the total resistance is reduced to 70 Ω. The extra
steps are not equal to 1 LSB and are not included in the INL,
DNL, R-INL, and R-DNL specifications.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation±8% Resistor Tolerance
The AD5116 operates in rheostat mode when only two terminals
are used as a variable resistor. The unused terminal can be
floating or tied to the W terminal as shown in Figure 42.
09657-040
W
A
B
W
A
B
W
A
B
Figure 42. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
R
AB
, is available in 5 kΩ, 10 , and 80 kΩ and has 64 tap points
accessed by the wiper terminal. The 6-bit data in the RDAC
latch is decoded to select one of the 64 possible wiper settings.
The general equation for determining the digitally programmed
output resistance between the W terminal and B terminal is:
BS
WB
RR
=
Bottom scale (1)
W
AB
WB
RR
D
DR +×=
64
)
(
From 0 to 64 (2)
where:
D is the decimal equivalent of the binary code in the 6-bit
RDAC register.
R
AB
is the end-to-end resistance.
R
BS
is the wiper resistance at bottom scale.
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, R
WA
.
R
WA
starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equation for
this operation is:
W
ABAW
RRR
+=
Bottom scale (3)
W
ABAW
RR
D
DR +×
=
64
64
)(
From 0 to 63 (4)
TS
AW
RR =
Top scale (5)
where:
D is the decimal equivalent of the binary code in the 6-bit
RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance.
R
TS
is the wiper resistance at top scale.
Regardless of which setting the part is operating in, take care
to limit the current between the A terminal to B terminal, W
terminal to A terminal, and W terminal to B terminal, to the
maximum continuous current or pulsed current specified in
Table 4. Otherwise, degradation or possible destruction of
the internal switch contact can occur.

AD5116BCPZ10-500R7

Mfr. #:
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Description:
Digital Potentiometer ICs SGL CH64-Position I2C
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