74ALVCH16374 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 9 July 2012 9 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
[1] All typical values are measured at T
amb
=25C.
[2] Typical values are measured at V
CC
= 2.5 V.
[3] Typical values are measured at V
CC
= 3.3 V.
[4] t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
t
dis
disable time nOE to nQn; see Figure 7
[4]
V
CC
= 1.2 V - 6.2 - ns
V
CC
= 1.8 V 1.5 3.1 5.4 ns
V
CC
= 2.3 V to 2.7 V
[2]
1.0 2.1 4.0 ns
V
CC
= 2.7 V 1.0 2.9 4.5 ns
V
CC
= 3.0 V to 3.6 V
[3]
1.0 2.6 4.1 ns
t
W
pulse width nCP HIGH or LOW; see Figure 6
V
CC
= 1.8 V 4.0 2.0 - ns
V
CC
= 2.3 V to 2.7 V
[2]
3.0 1.6 - ns
V
CC
= 2.7 V 3.0 1.6 - ns
V
CC
= 3.0 V to 3.6 V
[3]
2.5 1.4 - ns
t
su
set-up time Dn to nCP; see Figure 8
V
CC
= 1.8 V 1.5 0.2 - ns
V
CC
= 2.3 V to 2.7 V
[2]
1.2 0.2 - ns
V
CC
= 2.7 V 1.5 0.4 - ns
V
CC
= 3.0 V to 3.6 V
[3]
1.2 0.2 - ns
t
h
hold time Dn to nCP; see Figure 8
V
CC
= 1.8 V 0.6 0.2 - ns
V
CC
= 2.3 V to 2.7 V
[2]
0.8 0.1 - ns
V
CC
= 2.7 V 0.6 0.2 - ns
V
CC
= 3.0 V to 3.6 V
[3]
0.8 0.0 - ns
C
PD
power dissipation
capacitance
per flip-flop; V
I
=GNDtoV
CC
[5]
outputs enabled - 16 - pF
outputs disabled - 10 - pF
Table 7. Dynamic characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 9.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
