74ALVCH16374 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 9 July 2012 5 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
1OE
, 2OE 1, 24 output enable input (active LOW)
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 3-state flip-flop outputs
2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 3-state flip-flop outputs
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
V
CC
7, 18, 31, 42 positive supply voltage
1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs
2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs
1CP, 2CP 48, 25 clock input
Table 3. Function table
[1]
Inputs Internal
flip-flops
Outputs Q0 to Q7 Operating mode
nOE nCP Dn
L l L L load and read register
L hH H
H l L Z load register and disable outputs
H hH Z
