MC33368
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7
FUNCTIONAL DESCRIPTION
INTRODUCTION
With the goal of exceeding the requirements of legislation
on line current harmonic content, there is an ever increasing
demand for an economical method of obtaining a unity
power factor. This data sheet describes a monolithic control
IC that was specifically designed for power factor control
with minimal external components. It offers the designer a
simple cost effective solution to obtain the benefits of active
power factor correction.
Most electronic ballasts and switching power supplies use
a bridge rectifier and a bulk storage capacitor to derive raw
dc voltage from the utility ac line, Figure 14.
Figure 14. Uncorrected Power Factor Circuit
Rectifiers
Converter
Bulk
Storage
Capacitor
Load
AC
Line
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and results in
a high charge current spike, Figure 15. Since power is only
taken near the line voltage peaks, the resulting spikes of
current are extremely nonsinusoidal with a high content of
harmonics. This results in a poor power factor condition
where the apparent input power is much higher than the real
power. Power factor ratios of 0.5 to 0.7 are common.
Figure 15. Uncorrected Power Factor Input Waveform
s
Rectified
DC
0
V
pk
Line Sag
AC Line
Voltage
AC Line
Current
0
Power factor correction can be achieved with the use of
either a passive or active input circuit. Passive circuits
usually contain a combination of large capacitors, inductors,
and rectifiers that operate at the ac line frequency. Active
circuits incorporate some form of a high frequency
switching converter for the power processing with the boost
converter being the most popular topology. Since active
input circuits operate at a frequency much higher than that
of the ac line, they are smaller, lighter in weight, and more
efficient than a passive circuit that yields similar results.
With proper control of the preconverter, almost any complex
load can be made to appear resistive to the ac line, thus
significantly reducing the harmonic current content.
Operating Description
The MC33368 contains many of the building blocks and
protection features that are employed in modern high
performance current mode power supply controllers.
Referring to the block diagram in Figure 16, note that a
multiplier has been added to the current sense loop and that
this device does not contain an oscillator. A description of
each of the functional blocks is given below.
Error Amplifier
An Error Amplifier with access to the inverting input and
output is provided. The amplifier is a transconductance type,
meaning that it has high output impedance with controlled
voltage−to−current gain (g
m
50 mmhos). The noninverting
input is internally biased at 5.0 V ±2.0%. The output voltage
of the power factor converter is typically divided down and
monitored by the inverting input. The maximum input bias
current is −1.0 mA which can cause an output voltage error
that is equal to the product of the input bias current and the
value of the upper divider resistor R2. The Error Amplifier
output is internally connected to the Multiplier and is pinned
out (Pin 4) for external loop compensation. Typically, the
bandwidth is set below 20 Hz so that the amplifiers output
voltage is relatively constant over a given ac line cycle. In
effect, the error amplifier monitors the average output voltage
of the converter over several line cycles resulting in a fixed
Drive Output on−time. The amplifier output stage can sink
and source 11.5 mA of current and is capable of swinging from
1.7 to 5.0 V, assuring that the Multiplier can be driven over its
entire dynamic range.
Note that by using a transconductance type amplifier, the
input is allowed to move independently with respect to the
output, since the compensation capacitor is connected to
ground. This allows dual usage of the Voltage Feedback pin
by the Error Amplifier and Overvoltage Comparator.
Overvoltage Comparator
An Overvoltage Comparator is incorporated to eliminate
the possibility of runaway output voltage. This condition
can occur during initial startup, sudden load removal, or
during output arcing and is the result of the low bandwidth
that must be used in the Error Amplifier control loop. The
Overvoltage Comparator monitors the peak output voltage
of the converter, and when exceeded, immediately
terminates MOSFET switching. The comparator threshold
is internally set to 1.08 V
ref
. In order to prevent false tripping
during normal operation, the value of the output filter
capacitor C3 must be large enough to keep the peak−to−peak
ripple less than 16% of the average dc output.
MC33368
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8
Multiplier
A single quadrant, two input multiplier is the critical
element that enables this device to control power factor. The
ac haversines are monitored at Pin 5 with respect to ground
while the Error Amplifier output at Pin 4 is monitored with
respect to the Voltage Feedback Input threshold. A graph of
the Multiplier transfer curve is shown in Figure 2. Note that
both inputs are extremely linear over a wide dynamic range,
0 to 3.2 V for Pin 5 and 2.5 to 4.0 V for Pin 4. The Multiplier
output controls the Current Sense Comparator threshold as
the ac voltage traverses sinusoidally from zero to peak line.
This has the effect of forcing the MOSFET on−time to track
the input line voltage, thus making the preconverter load
appear to be resistive.
Pin 6 Threshold [ 0.55
ǒ
V
Pin 4
–V
Pin 3
Ǔ
V
Pin 5
Zero Current Detector
The MC33368 operates as a critical conduction current
mode controller, whereby output switch conduction is
initiated by the Zero Current Detector and terminated when
the peak inductor current reaches the threshold level
established by the Multiplier output. The Zero Current
Detector initiates the next on−time by setting the R
S
Latch
at the instant the inductor current reaches zero. This critical
conduction mode of operation has two significant benefits.
First, since the MOSFET cannot turn−on until the inductor
current reaches zero, the output rectifiers reverse recovery
time becomes less critical allowing the use of an inexpensive
rectifier. Second, since there are no deadtime gaps between
cycles, the ac line current is continuous thus limiting the
peak switch to twice the average input current
The Zero Current Detector indirectly senses the inductor
current by monitoring when the auxiliary winding voltage
falls below 1.2 V. To prevent false tripping, 200 mV of
hysteresis is provided. The Zero Current Detector input is
internally protected by two clamps. The upper 10 V clamp
prevents input overvoltage breakdown while the lower
−0.7 V clamp prevents substrate injection. An external
resistor must be used in series with the auxiliary winding to
limit the current through the clamps to 5.0 mA or less.
Current Sense Comparator and RS Latch
The Current Sense Comparator R
S
Latch configuration
used ensures that only a single pulse appears at the Drive
Output during a given cycle. The inductor current is
converted to a voltage by inserting a ground−referenced
sense resistor R7 in series with the source of output switch.
This voltage is monitored by the Current Sense Input and
compared to a level derived from the Multiplier output. The
peak inductor current under normal operating conditions is
controlled by the threshold voltage of Pin 6 where:
I
pk
+
Pin 6 Threshold
R7
Abnormal operating conditions occur when the
preconverter is running at extremely low line or if output
voltage sensing is lost. Under these conditions, the Current
Sense Comparator threshold will be internally clamped to
1.5 V. Therefore, the maximum peak switch current is:
I
pk(max)
+
1.5 V
R7
With the component values shown in Figure 16, the
Current Sense Comparator threshold, at the peak of the
haversine, varies from 110 mV at 90 Vac to 100 mV at
268 Vac. The Current Sense Input to Drive Output
propagation delay is typically 200 ns.
Timer
A watchdog timer function was added to the IC to
eliminate the need for an external oscillator when used in
stand alone applications. The Timer provides a means to
automatically start or restart the preconverter if the Drive
Output has been off for more than 385 ms after the inductor
current reaches zero.
Undervoltage Lockout and Quickstart
The MC33368 has a 5.0 V internal reference brought out
to Pin 1 and capable of sourcing 10 mA typically. It also
contains an Undervoltage Lockout (UVLO) circuit which
suppresses the Gate output at Pin 11 if the V
CC
supply
voltage drops below 8.5 V typical.
A Quickstart circuit has been incorporated to optimize
converter startup. During initial startup, compensation
capacitor C1 will be discharged, holding the Error Amplifier
output below the Multipliers threshold. This will prevent
Drive Output switching and delay bootstraping of capacitor
C4 by diode D6. If Pin 4 does not reach the multiplier
threshold before C4 discharges below the lower SMPS
UVLO threshold, the converter will hiccup and experience
a significant startup delay. The Quickstart circuit is designed
to precharge C1 to 1.7 V. This level is slightly below the
Pin 4 Multiplier threshold, allowing immediate Drive
Output switching.
Restart Delay
A restart delay pin is provided to allow hiccup mode fault
protection in case of a short circuit condition and to prevent
the SMPS from repeatedly trying to restart after the input
line voltage has been removed. When power is first applied,
there is no startup delay, but subsequent cycling of the V
CC
voltage will result in delay times that are programmed by an
external resistor and capacitor. The Restart Delay, Pin 2, is
a high impedance, so that an external capacitor can provide
delay times as long as several seconds.
If the SMPS output is short circuited, the transformer
winding, which provides the V
CC
voltage to the control IC
and the MC33368, will be unable to sustain V
CC
to the
control circuits. The restart delay capacitor at Pin 2 of the
MC33368 prevents the high voltage startup transistor within
the IC from maintaining the voltage on C4. After V
CC
drops
below the UVLO threshold in the SMPS, the SMPS
switching transistors are held off for the time programmed
by the values of the restart capacitor (C9) and resistor (R8).
In this manner, the SMPS switching transistors are operated
MC33368
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9
at very low duty cycles, preventing their destruction. If the
short circuit fault is removed, the power supply system will
turn on by itself in a normal startup mode after the restart
delay has timed out.
Output Switching Frequency Clamp
In normal operation, the MC33368 operates the boost
inductor in the critical mode. That is, the inductor current
ramps to a peak value, ramps down to zero, then
immediately begins ramping positive again. The peak
current is programmed by the multiplier output within the
IC. As the input voltage haversine declines to near zero, the
output switch on−time becomes constant, rather than going
to zero because of the small integrated dc voltage at Pin 5
caused by C2, R3 and R5. Because of this, the average line
current does not exactly follow the line voltage near the zero
crossings. The Output Switching Frequency Clamp
remedies this situation to improve power factor and
minimize EMI generated in this operating region. The
values of R10 and C7, as shown in Figure 16, program a
minimum off−time in the frequency clamp which overrides
the zero current detect signal, forcing a minimum off−time.
This allows discontinuous conduction operation of the boost
inductor in the zero crossing region, and the average line
current more nearly follows the voltage. The Output
Switching Frequency Clamp function can be disabled by
connecting the FC input, Pin 13, to the V
CC
supply Pin 12.
For best results, the minimum off−time, determined by the
values of R10 and C7, should be chosen so that t
s(min)
= t
(on)
+ t
(off)fc
. Output drive is inhibited when the voltage at the
frequency clamp input is less than 2.0 V. When the output
drive is high, C7 is discharged through an internal 100 mA
current source. When the output drive switches low, C7 is
charged through R10. The drive output is inhibited until the
voltage across C7 reaches 2.0 V, establishing a minimum
off−time where:
t
(off)fc
+*R10 C7 log
e
ƪ
1 *
ǒ
2
V
CC
Ǔ
ƫ
Output
The IC contains a CMOS output driver that was
specifically designed for direct drive of power MOSFETs.
The Gate Output is capable of up to ±1500 mA peak current
with a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the Gate
Output in a sinking mode whenever the Undervoltage
Lockout is active. This characteristic eliminates the need for
an external gate pull−down resistor. The totem−pole output
has been optimized to minimize cross−conduction current
during high speed operation.

MC33368DG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC High Voltage PFC w/Critical Mode
Lifecycle:
New from this manufacturer.
Delivery:
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