74AUP2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 11 February 2013 9 of 21
NXP Semiconductors
74AUP2G38
Low-power dual 2-input NAND gate; open drain
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PZL
and t
PLZ
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N where:
f
i
= input frequency in MHz;
V
CC
= supply voltage in V;
N = number of inputs switching.
12. Waveforms
C
L
= 5 pF, 10 pF, 15 pF and 30 pF
C
PD
power dissipation
capacitance
f = 1 MHz; V
I
= GND to V
CC
[3]
V
CC
= 0.8 V - 0.6 - - - - pF
V
CC
= 1.1 V to 1.3 V - 0.7 - - - - pF
V
CC
= 1.4 V to 1.6 V - 0.8 - - - - pF
V
CC
= 1.65 V to 1.95 V - 0.9 - - - - pF
V
CC
= 2.3 V to 2.7 V - 1.1 - - - - pF
V
CC
= 3.0 V to 3.6 V - 1.4 - - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
(85 C)
Max
(125 C)
Measurement points are given in Table 9.
Logic level V
OL
is a typical output voltage level that occurs with the output load.
Fig 8. The data input (nA, nB) to output (nY) propagation delays
mnb132
t
PLZ
V
X
nY output
nA, nB input
V
I
V
CC
V
M
V
OL
GND
t
PZL
V
M
Table 9. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
V
X
0.8 V to 1.6 V 0.5V
CC
0.5V
CC
V
OL
+0.1V
1.65 V to 2.7 V 0.5V
CC
0.5V
CC
V
OL
+0.15V
3.0 V to 3.6 V 0.5V
CC
0.5V
CC
V
OL
+0.3V
