18
LTC1430A
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Figure 17 is a synchronous buck regulator designed to
provide a low voltage, very high current output from a 5V
or lower input voltage. The circuit uses two 8-pin
LTC1430ACS8s, operated 180° out of phase from each
other. Each half of the circuit is good for 15A of output
current, giving 30A total. The LT
®
1006 amplifier forces the
two half circuits to share the load current equally. This
scheme trades a small amount of additional control circuit
complexity for radical reductions in the volume (hence
cost) of the capacitors and inductors required. Advan-
tages of this approach include very low input and output
ripple voltages, higher ripple frequency and extremely fast
transient response.
By incorporating two regulators phased opposite one
another, both the input ripple currents and the output
ripple currents tend to cancel. This permits running much
higher ripple currents in the output inductors than would
be tolerable with a single channel. The overall output ripple
current in a two phase design is approximately 1/2 of a
single channel’s ripple current, allowing the inductor value
of each channel to be 1/2 that of what a single channel
system would require for equal output ripple. Since energy
storage varies as the square of inductor current, and
directly as the inductance, each inductor stores only 1/8th
the energy of a single inductor design. Since there are two
inductors, total energy storage, and therefore inductor
volume, is 1/4th that of a single phase system.
A similar analysis can be done for the input capacitor
requirements. In fact, a two-phase regulator will actually
require less input capacitance than a single channel design
at 1/2 the load current. Figure 16 shows how the ripple
currents tend to cancel one another.
Another significant advantage of the two-phase topology
is radically improved transient response. During a load
transient, each of the two channels runs to maximum (or
minimum) duty cycle. The two ripple current terms now
end up reinforcing one another rather than canceling. The
result is a very high di/dt, hence, very fast transient
recoveries. Once steady state conditions return, the ripple
currents begin to cancel again, providing very low output
ripple voltage.
A + B
CHANNEL A
CHANNEL B
2µs/DIV
1430A F16
The clocking of the two channels is accomplished by the
CD4047, a low cost, CMOS mulitvibrator with a built-in
divide-by-two flip flop. The CD4047 oscillator is set to run
at 600kHz and the Q and Q outputs drive the LTC1430A
shutdown pins. Since the sync signals are derived from
the clock’s divide-by-two outputs, they are inherently
180° out of phase and at the desired 300kHz clock fre-
quency. Q1, D1 and the two resistors connected to Q1’s
base are used to disable the synchronization at turn-on to
prevent start-up problems. As long as the input-output
differential voltage is large enough to turn on Q1, the sync
circuit is disabled and both LTC1430As will free run at
200kHz. Once the output rises above ≈1.5V, the regula-
tors are allowed to lock to the clock.
One challenge with a voltage mode two-phase design is
current sharing. Unlike current mode control which offers
inherent current sharing, voltage mode control virtually
assures that one channel will try to hog a large percentage
of the load current. The circuit gets around this problem
with a current share amplifier. The LT1006 op amp com-
pares the voltage across both sense resistors and adds or
subtracts a small current into the lower LTC1430A’s
feedback divider, forcing it to match the upper LTC1430A’s
current. The two PCB trace resistors are intentionally
chosen to have a very low value to minimize power losses.
The LT1006 features 80µV typical V
OS
, ensuring reason-
ably accurate current sharing.
There are three problems associated with this current
sharing approach that must be dealt with. The first is that
Figure 16. Output Inductor Currents 5A/DIV, 30A Out
