Rev A 6/10/15 2 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844004-104 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels.
3 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
4 nPLL_SEL Input Pulldown
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
5, 6, 7, 8, 15,
16, 20, 21,
28, 29
nc Unused No connect.
9V
DDA
Power Analog supply pin.
10,
12
F_SEL0,
F_SEL1
Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
11 V
DD
Power Core supply pin.
13,
14
XTAL_OUT
XTAL_IN
Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
17, 22 GND Power Power supply ground.
18 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
19 nXTAL_SEL Input Pulldown
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels.
25, 32 V
DDO
Power Output supply pins.
26, 27 Q2, nQ2 Output Differential output pair. LVDS interface levels.
30, 31 nQ1, Q1 Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
