FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 13 Rev A 6/10/15
844004-104 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 844004-104.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844004-104 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (105mA + 12mA) = 405.4mW
Power (outputs)
MAX
= V
DDO_MAX
* I
DDO_MAX
= 3.465V * 120mA = 415.8mW
Total Power_
MAX
= 405.4mW + 415.8mW = 821.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 42.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.821W * 42.4°C/W = 104.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 7. Thermal Resistance
JA
for 32 Lead VFQFN, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 42.4°C/W 37.0°C/W 33.2°C/W
Rev A 6/10/15 14 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844004-104 DATA SHEET
Reliability Information
Table 8.
JA
vs. Air Flow Table for a 32 Lead VFQFN
Transistor Count
The transistor count for 844004-104 is: 2914
Package Outline and Package Dimensions
Package Outline - K Suffix for VFQFN Packages
Table 9. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This
drawing is not intended to convey the actual pin count or pin layout
of this device. The pin count and pinout are shown on the front
page. The package dimensions are in Table 8 below.
JA
vs. Air Flow
Meter per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 42.4°C/W 37.0°C/W 33.2°C/W
To p View
Index Area
D
Cham fer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A3
A1
S eating Plane
E2
E2
2
L
(N
-1)x e
(Ref.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Ba se
N
OR
Anvil
Singulation
or
Sawn
Singulation
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 32
A 0.80 1.00
A1 00.05
A3 0.25 Ref.
b 0.18 0.25 0.30
N
D
& N
E
8
D & E 5.00 Basic
D2 & E2 3.0 3.3
e 0.50 Basic
L 0.30 0.40 0.50
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 15 Rev A 6/10/15
844004-104 DATA SHEET
Ordering Information
Table 10. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
844004AK-104LF ICS004A104L “Lead-Free” 32 Lead VFQFN Tray 0C to 70C
844004AK-104LFT ICS004A104L “Lead-Free” 32 Lead VFQFN Tape & Reel 0C to 70C

844004AK-104LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVDS OUTPUT PLL CLK SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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