CY2CC910OXI-1T

CY2CC910
1:10 Clock Fanout Buffer
Cypress Semiconductor Corporation 198 Champion Court San Jose
,
CA 95134-1709 408-943-2600
Document #: 38-07348 Rev. *D Revised March 18, 2010
Features
Low voltage operation
Full range support:
3.3V
2.5V
1.8V
Over voltage tolerant input hot swappable
1:10 Fanout
Drives either a 50-Ohm or 75-Ohm load
Low input capacitance
Low output skew
Low propagation delay
Typical (t
pd
less than 4 ns)
High speed operation:
200 MHz at1.8V
650 MHz at 2.5V and 3.3V
Industrial versions available
Available in SSOP package
Description
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the
industry’s fastest logic and buffers.
The Cypress CY2CC910 fanout buffer features one input and 10
outputs. It is ideal for conversion from and to 3.3V, 2.5V, and 1.8V
Designed for Data Communications clock management applica-
tions, the large fanout from a single input reduces loading on the
input clock.
Cypress employs the unique AVCMOS type outputs VOI
(Variable Output Impedance) that dynamically adjust for variable
impedance matching, eliminate the need for series damping
resistors, and reduce overall noise.
OUTPUT
(AVCMOS)
IN
3
11
14
12
9
7
5
16
18
19
Q1
Q5
Q7
Q6
Q4
Q3
Q2
Q8
Q9
Q10
GND
VDD
INPUT
(AVCMOS)
2,6,10
13,17
4,8
15,20
1
Logic Block Diagram
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CY2CC910
Document #: 38-07348 Rev. *D Page 2 of 10
Maximum Ratings
[1]
Storage Temperature:................................. –65°C to +150°C
Ambient Temperature: .................................. –40°C to +85°C
Supply Voltage to Ground Potential
V
CC
...................................................................–0.5V to 4.6V
Input..................................................................–0.5V to 5.8V
Supply Voltage to Ground Potential
(Outputs only)........................................... –0.5V to V
DD
+ 1V
DC Output Voltage.................................... –0.5V to V
DD
+ 1V
Power Dissipation........................................................0.75W
Pin Configuration
Figure 1. 20-Pin SOIP-SSOP
Pin Description
Pin Number Pin Name Description
1 IN Input
2,6,10,13,17
G
ND Ground
4,8,15,20
V
DD
Power Supply
3,5,7,9,11,12,14,16,18,19 Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10 Output
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CY2CC910
20 pin SOIC/SSOP
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
Note
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
[+] Feedback
CY2CC910
Document #: 38-07348 Rev. *D Page 3 of 10
Variable Output Impedance Control (VOI)
Figure 2. Output Voltage versus Output Current (T
A
= 25°C)
Pull Down
0
0.5
1
1.5
2
2.5
3
3.5
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Iol (A)
Vdd = 3.3 V Vdd = 2.5 V Vdd = 1.8 V
DC Electrical Characteristics
At 3.3V
(See Figure 3)
Parameter Description Conditions Min Typ Max Unit
V
OH
Output High Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= –12 mA 2.3 3.3 V
V
OL
Output Low Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA 0.2 0.5 V
V
IH
Input High Voltage Guaranteed Logic High
Level
25.8V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max. V
IN
= 2.7V 1 μA
I
IL
Input Low Current V
DD
= Max. V
IN
= 0.5V –1 μA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(Max.) 20 μA
V
IK
Clamp Diode Voltage V
DD
= Min., I
IN
= –18 mA –0.7 –1.2 V
I
OK
Continuous Clamp Current V
DD
= Max., V
OUT
= GND –50 mA
O
OFF
Power-down Disable V
DD
= GND, V
OUT
= < 4.5V 100 μA
V
H
Input Hysteresis 80 mV
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CY2CC910OXI-1T

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:10 650MHZ 20SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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