CY2CC910OXI-1T

CY2CC910
Document #: 38-07348 Rev. *D Page 4 of 10
At 2.5V
(See Figure 3)
Parameter Description Conditions Min Typ Max Unit
V
OH
Output High Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= –7 mA 1.8 V
I
OH
= 12 mA 1.6 V
V
OL
Output Low Voltage V
DD
= Min., V
IN
= V
IH
or V
IL
I
OL
= 12 mA 0.65 V
V
IH
Input High Voltage Guaranteed Logic High Level 1.6 5.0 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max. V
IN
= 2.4V 1 μA
I
IL
Input Low Current V
DD
= Max. V
IN
= 0.5V –1 μA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(Max.) 20 μA
V
IK
Clamp Diode Voltage V
DD
= Min., I
IN
= –18 mA –0.7 –1.2 V
I
OK
Continuous Clamp Current V
DD
= Max., V
OUT
= GND –50 mA
O
OFF
Power Down Disable V
DD
= GND, V
OUT
= < 4.5V 100 μA
V
H
Input Hysteresis 80 mV
At 1.8V
(See Figure 7)
Parameter Description Test Condition
[2]
Min Max Unit
V
DD
Supply Voltage 1.71 1.89 V
V
IH
Input High Voltage 0.65V
DD
[1.1] 4.3 V
V
IL
Input Low Voltage –0.3 0.35 V
DD
[0.6] V
V
OH
Output High Voltage I
OH
= –2 mA V
DD
– 0.45[1.2] V
V
OL
Output Low Voltage I
OH
= 2 mA 0.45 V
Capacitance
Parameter Description Test Conditions Typ Max Unit
C
IN
Input Capacitance V
IN
= 0V 2.5 pF
C
OUT
Output Capacitance V
OUT
= 0V 6.5 pF
Power Supply Characteristics
(See Figure 3)
Parameter Description Test Conditions Min Typ Max Unit
Δ
ICC
Delta I
CC
Quiescent Power
Supply Current
(I
DD
@ V
DD
= Max and V
IN
= V
DD
) – (I
DD
@ V
DD
= Max and V
IN
= V
DD
– 0.6V)
50 μA
I
CCD
Dynamic Power Supply
Current
V
DD
= Max
Input toggling 50% Duty Cycle, Outputs
Open
0.63 mA/
MHz
I
C
Total Power Supply Current V
DD
= Max
Input toggling 50% Duty
Cycle, Outputs Open fL = 40 MHZ
25 mA
Note
2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency.
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CY2CC910
Document #: 38-07348 Rev. *D Page 5 of 10
High Frequency Parametrics
Parameter Description Test Conditions Min Typ Max Unit
D
J
Jitter, Deterministic 50% duty cycle t
W
(50–50)
The “point to point load circuit”
| Output Jitter – Input Jitter |
See Figure 5 20 ps
F
max
3.3V
Maximum frequency
V
DD
= 3.3V
50% duty cycle t
W
(50–50)
Standard Load Circuit.
See Figure 3 160 MHz
50% duty cycle t
W
(50–50)
The “point to point load circuit”
See Figure 5 650
F
max
2.5V
Maximum frequency
V
DD
= 2.5V
The “point-to-point load circuit”
V
IN
= 2.4V/0.0V V
OUT
= 1.7V/0.7V
See Figure 5 200 MHz
F
max
1.8V
Maximum frequency
V
DD
= 1.8V
The “6-pF load circuit”
V
IN
= 1.7/0.0V V
OUT
= 1.2V/0.4V
See Figure 7 200 MHz
F
max(20)
Maximum frequency
V
DD
= 3.3V
20% duty cycle t
W
(20-80)
The “point to point load circuit”
V
IN
= 3.0V/0.0V V
OUT
= 2.3V/0.4V
See Figure 6 250 MHz
t
W
3.3V
Minimum pulse
V
DD
= 3.3V
The “point-to-point load circuit”
V
IN
= 3.0V/0.0V F = 100 MHz
V
OUT
= 2.0V/0.8V
See Figure 5 1ns
t
W
2.5V
Minimum pulse
V
DD
= 2.5V
The “point-to-point load circuit”
V
IN
= 2.4V/0.0V F = 100 MHz
V
OUT
= 1.7V/0.7V
See Figure 5 1ns
t
W
1.8V
Minimum pulse
V
DD
= 1.8V
The “6-pF load circuit”
V
IN
= 1.7V/0.0V V
OUT
= 1.2V/0.4V
See Figure 7 1ns
AC Switching Characteristics
At 3.3V (V
DD
= 3.3V ± 5%, Temperature = –40°C to +85°C)
Parameter Description Min Typ Max Unit
t
PLH
Propagation Delay – Low to High See Figure 4 1.5 2.7 3.5 ns
t
PHL
Propagation Delay – High to Low 1.5 2.7 3.5 ns
t
R
Output Rise Time 0.8 V/ns
t
F
Output Fall Time 0.8 V/ns
t
SK(0)
Output Skew: Skew between outputs of the same package (in
phase).
See Figure 11 0.2 ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same
output (t
PHL
– t
PLH
).
See Figure 10 0.2 ns
t
SK(t)
Package Skew: Skew between outputs of different packages at
the same power supply voltage, temperature and package type.
See Figure 12 0.4 ns
At 2.5V (V
DD
= 2.5V ± 5%, Temperature = –40°C to +85°C)
Parameter Description Min Typ Max Unit
t
PLH
Propagation Delay – Low to High See Figure 4 1.5 2.7 3.5 ns
t
PHL
Propagation Delay – High to Low 1.5 2.7 3.5 ns
t
R
Output Rise Time 0.8 V/ns
t
F
Output Fall Time 0.8 V/ns
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase). See Figure 11 0.2 ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output (t
PHL
– t
PLH
).
See Figure 10 0.2 ns
t
SK(t)
Package Skew: Skew between outputs of different packages at the same
power supply voltage, temperature and package type.
See Figure 12 0.4 ns
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CY2CC910
Document #: 38-07348 Rev. *D Page 6 of 10
Parameter Measurement Information: V
DD
at 3.3V to 2.5V
Figure 3. Load Circuit
[3,4,5]
Figure 4. Voltage Waveforms Propagation Delay Times
[6]
Figure 5. Point to Point Load Circuit
[3,4,5]
Figure 6. Voltage Waveforms – Pulse Duration
[4]
AC Switching Characteristics
At 1.8V(V
DD
= 1.8V ±5%, Temperature = –40°C to +85°C)
Parameter Description Min Typ Max Unit
t
PLH
Propagation Delay – Low to High See Figure 8 1.5 2.7 3.5 ns
t
PHL
Propagation Delay – High to Low 1.5 2.7 3.5 ns
t
R
Output Rise Time 20 – 80% 0.2 1.5 ns
t
F
Output Fall Time 20 – 80% 0.2 1.5 ns
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase). See Figure 11 0.2 ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output (t
PHL
– t
PLH
).
See Figure 10
0.2 ns
t
SK(t)
Package Skew: Skew between outputs of different packages at the same
power supply voltage, temperature and package type.
See Figure 12
0.4 ns
From Output
Under Test
C
L
= 50 pF
500 ohm
VDD/ 2
t
PLH
t
PHL
V
OH
V
OL
0 VInput
Out put
VDD/2
VDD/ 2
VDD/ 2
0.8VDD
From Output
Under Test
C
L
= 3 pF
500 ohm
0 V
Input
t
w(20-80)
0.8VDD
0 V
VDD/2
Input
t
w(50-50)
VDD/2
VDD/2
0.8VDD
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CY2CC910OXI-1T

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:10 650MHZ 20SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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