XA Artix-7 FPGAs Data Sheet: Overview
DS197 (v1.2) February 23, 2017 www.xilinx.com
Product Specification 7
This block is highly configurable to system design requirements and can operate 1, 2, or 4 lanes at the 2.5 Gb/s and 5.0 Gb/s
data rates. For high-performance applications, advanced buffering techniques of the block offer a flexible maximum payload
size of up to 1,024 bytes. The integrated block interfaces to the integrated high-speed transceivers for serial connectivity and
to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and Transaction
Layer of the PCI Express protocol.
Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various building blocks (the
integrated block for PCI Express, the transceivers, block RAM, and clocking resources) into an Endpoint or Root Port
solution. The system designer has control over many configurable parameters: lane width, maximum payload size, FPGA
logic interface speeds, reference clock frequency, and base address register decoding and filtering.
Xilinx offers two wrappers for the integrated block: AXI4-Stream and AXI4 (memory mapped). Note that legacy TRN/Local
Link is not available in 7 series devices for the integrated block for PCI Express. AXI4-Stream is designed for existing
customers of the integrated block and enables easy migration to AXI4-Stream from TRN. AXI4 (memory mapped) is
designed for Xilinx Platform Studio/EDK design flow and MicroBlaze™ processor based designs.
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
.
Configuration
There are many advanced configuration features, including:
• High-speed SPI and BPI (parallel NOR) configuration
• Built-in MultiBoot and safe-update capability
• 256-bit AES encryption with HMAC/SHA-256 authentication
• Built-in SEU detection and correction
• Partial reconfiguration
The XA Artix-7 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits
is between 10 Mb and 31 Mb, depending on device size and user-design implementation options. The configuration storage
is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling
the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available, determined by the
three mode pins.
The SPI interface (x1, x2, and x4 modes) and the BPI interface (parallel-NOR x8 and x16) are two common methods used
for configuring the FPGA. Users can directly connect an SPI or BPI flash to the FPGA, and the FPGA's internal configuration
logic reads the bitstream out of the flash and configures itself. The FPGA automatically detects the bus width on the fly,
eliminating the need for any external controls or switches. Bus widths supported are x1, x2, and x4 for SPI, and x8 and x16
for BPI. The larger bus widths increase configuration speed and reduce the amount of time it takes for the FPGA to start up
after power-on. Note that BPI is not supported in the CPG236 package used by XA7A12T, XA7A15T, XA7A25T, XA7A35T,
and XA7A50T.
In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for higher speed
configuration, the FPGA can use an external configuration clock source. This allows high-speed configuration with the ease
of use characteristic of master mode. Slave modes up to 32 bits wide are also supported by the FPGA that are especially
useful for processor-driven configuration.
The FPGA has the ability to reconfigure itself with a different image using SPI or BPI flash, eliminating the need for an
external controller. The FPGA can reload its original design in case there are any errors in the data transmission, ensuring
an operational FPGA at the end of the process. This is especially useful for updates to a design after the end product has
been shipped. Customers can ship their products with an early version of the design, thus getting their products to market
faster. This feature allows customers to keep their end users current with the most up-to-date designs while the product is
already in the field.
The dynamic reconfiguration port (DRP) gives the system designer easy access to the configuration and status registers of
the MMCM, PLL, XADC, transceivers, and integrated block for PCI Express. The DRP behaves like a set of memory-mapped
registers, accessing and modifying block-specific configuration bits as well as status and control registers.
