AD7887BR-REEL Datasheet AD7887ARMZ, AD7887BRZ, AD7887WARMZ | P13-P15

AD7887 Data Sheet

ANALOG INPUT

Figure 12 shows an equivalent circuit of the analog input

structure of the AD7887. The two diodes, D1 and D2, provide

ESD protection for the analog inputs. Care must be taken to

ensure that the analog input signal never exceed the supply rails

by more than 200 mV. Exceeding this value causes the diodes

to become forward biased and to start conducting into the

substrate. The maximum current these diodes can conduct

without causing irreversible damage to the part is 20 mA.

However, it is worth noting that a small amount of current

(1 mA) being conducted into the substrate due to an

overvoltage on an unselected channel can cause inaccurate

conversions on a selected channel. Capacitor C1 in Figure 12 is

typically about 4 pF and can primarily be attributed to pin

capacitance. Resistor R1 is a lumped component made up of the

on resistance of a multiplexer and a switch. This resistor is

typically about 100 Ω. Capacitor C2 is the ADC sampling

capacitor and typically has a capacitance of 20 pF.

Note that the analog input capacitance seen when in track mode

is typically 38 pF, whereas in hold mode it is typically 4 pF.

4pF

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

20pF

06191-012

Figure 12. Equivalent Analog Input Circuit

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC

low-pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance

source. Large source impedances will significantly affect the ac

performance of the ADC. This may necessitate the use of an

input buffer amplifier. The choice of op amp is a function of the

particular application.

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases and performance degrades.

Figure 13 shows a graph of the total harmonic distortion vs. the

analog input signal frequency for different source impedances.

INPUT FREQUENCY (kHz)

–90

41.24

THD (dB)

10.89 31.5921.14

–85

–80

–75

–70

–65

49.86

THD vs. FREQUENCY FOR DIFFERENT

SOURCE IMPEDANCES

= 5V

5V EXT REFERENCE

= 1k

Ω, C

= 100pF

= 50

Ω, C

= 2.2nF

= 10Ω

, C

= 10nF

06191-013

Figure 13. THD vs. Analog Input Frequency

On-Chip Reference

The AD7887 has an on-chip 2.5 V reference. This reference can

be enabled or disabled by clearing or setting the REF bit in the

control register, respectively. If the on-chip reference is to be used

externally in a system, it must be buffered before it is applied

elsewhere. If an external reference is applied to the device, the

internal reference is automatically overdriven. However, it is

advised to disable the internal reference by setting the REF bit

in the control register when an external reference is applied in

order to obtain optimum performance from the device. When

the internal reference is disabled, SW1, shown in Figure 14,

opens and the input impedance seen at the AIN1/V

REF

pin is the

input impedance of the reference buffer, which is in the region

of gigaohms. When the internal reference is enabled, the input

impedance seen at the pin is typically 10 kΩ. When the AD7887

is operated in two-channel mode, the reference is taken from

internally, not from the on-chip 2.5 V reference.

2.5V

10kΩ

SW1

AIN1/V

REF

06191-014

Figure 14. On-Chip Reference Circuitry

Rev. E | Page 12 of 24

Data Sheet AD7887

POWER-DOWN OPTIONS

The AD7887 provides flexible power management to allow

the user to achieve the best power performance for a given

throughput rate.

The power management options are selected by programming

the power management bits (that is, PM1 and PM0) in the

control register. Table 6 summarizes the available options.

When the power management bits are programmed for either

of the auto power-down modes, the part enters power-down

mode on the 16

rising SCLK edge after the falling edge of

The first falling SCLK edge after the

falling edge causes the

part to power up again. When the

AD7887 is in Mode 1, that is,

PM1 = PM0 = 0, the part enters shutdown on the rising edge of

and power up from shutdown on the falling edge of

. If

is brought high during the conversion in this mode, the part

immediately enters shutdown.

Power-Up Times

The AD7887 has an approximate 1 μs power-up time when

powering up from standby or when using an external reference.

When V

is first connected the AD7887 powers up in Mode 1,

that is, PM1 = PM0 = 0. The part is put into shutdown on the

rising edge of

in this mode. A subsequent power-up from

shutdown takes approximately 5 μs. The AD7887 wake-up time

is very short in the autostandby mode; therefore, it is possible to

wake up the part and carry out a valid conversion in the same

read/write operation.

POWER VS. THROUGHPUT RATE

By operating the AD7887 in autoshutdown mode, autostandby

mode, or Mode 1, the average power consumption of the

AD7887 decreases at lower throughput rates. Figure 15 shows

how as the throughput rate is reduced, the device remains in its

power-down state longer and the average power consumption

over time drops accordingly.

For example, if the AD7887 is operated in a continuous sampling

mode with a throughput rate of 10 kSPS and a SCLK of 2 MHz

= 5 V), PM1 = 1 and PM0 = 0, that is, the device is in auto-

shutdown mode, and the on-chip reference is used, the power

consumption is calculated as follows: The power dissipation

during normal operation is 3.5 mW (V

= 5 V). If the power-up

time is 5 μs and the remaining conversion plus acquisition time

is 15.5 t

SCLK

, that is, approximately 7.75 μs (see Figure 18), the

AD7887 can be said to dissipate 3.5 mW for 12.75 μs during

each conversion cycle. If the throughput rate is 10 kSPS, the

cycle time is 100 μs and the average power dissipated during

each cycle is (12.75/100) × (3.5 mW) = 446.25 μ W. I f V

= 3 V,

SCLK = 2 MHz, and the device is in autoshutdown mode using the

on-chip reference, the power dissipation during normal operation

is 2.1 mW. The AD7887 can now be said to dissipate 2.1 mW

for 12.75 μs during each conversion cycle. With a throughput

rate of 10 kSPS, the average power dissipated during each cycle

is (12.75/100) × (2.1 mW) = 267.75 μW. Figure 15 shows the

power vs. throughput rate for automatic shutdown with both

5 V and 3 V supplies.

THROUGHPUT RATE (kSPS)

POWER (mW)

0.1

0.01

= 5V

SCLK = 2MHz

= 3V

SCLK = 2MHz

20 504030

06191-015

Figure 15. Power vs. Throughput Rate

MODES OF OPERATION

The AD7887 has several modes of operation that are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for differing application requirements. The modes of

operation are controlled by the PM1 and PM0 bits of the control

of the AD7887, the default mode of all 0s in the control register

can be set up by tying the DIN line permanently low.

Mode 1 (PM1 = 0, PM0 = 0)

This mode allows the user to control the powering down of the

part via the

pin. Whenever

is low, the AD7887 is fully

powered up; whenever

is high, the AD7887 is in full

shutdown. When

goes from high to low, all on-chip circuitry

starts to power up. It takes approximately 5 μs for the AD7887

internal circuitry to be fully powered up. As a result, a

conversion (or sample-and-hold acquisition) should not be

initiated during this 5 μs.

Figure 16 shows a general diagram of the operation of the

AD7887 in this mode. The input signal is sampled on the

second rising edge of SCLK following the

falling edge. The

user should ensure that 5 μs elapses between the falling edge of

and the second rising edge of SCLK. In microcontroller

applications, this is readily achievable by driving the

input

from one of the port lines and ensuring that the serial data read

(from the microcontrollers serial port) is not initiated for 5 μs.

In DSP applications, where

is generally derived from the

serial frame synchronization line, it is usually not possible to

separate the

falling edge and second SCLK rising edge by up

to 5 μs without affecting the speed of the rest of the serial clock.

Therefore, the user must write to the control register to exit this

mode and (by writing PM1 = 0 and PM0 = 1) put the part into

Mode 2, that is, normal mode. A second conversion needs to be

initiated when the part is powered up to get a conversion result.

The write operation that takes place in conjunction with this

Rev. E | Page 13 of 24

AD7887 Data Sheet

second conversion can put the part back into Mode 1, and the

part goes into power-down mode when

returns high.

Mode 2 (PM1 = 0, PM0 = 1)

In this mode of operation, the AD7887 remains fully powered

up regardless of the status of the

line. It is intended for fastest

throughput rate performance because the user does not have to

worry about the 5 μs power-up time previously mentioned.

Figure 17 shows the general diagram of the operation of the

AD7887 in this mode.

The data presented to the AD7887 on the DIN line during the

first eight clock cycles of the data transfer are loaded to the

control register. To continue to operate in this mode, the user

must ensure that PM1 is loaded with 0 and PM0 is loaded with

1 on every data transfer.

The falling edge of

initiates the sequence, and the input

signal is sampled on the second rising edge of the SCLK input.

Sixteen serial clock cycles are required to complete the conversion

and access the conversion result. Once a data transfer is complete

(that is, once

returns high), another conversion can be initiated

immediately by bringing

low again.

Mode 3 (PM1 = 1, PM0 = 0)

In this mode, the AD7887 automatically enters its full shutdown

mode at the end of every conversion. It is similar to Mode 1

except that the status of

does not have any effect on the

power-down status of the AD7887.

Figure 18 shows the general diagram of the operation of the

AD7887 in this mode. On the first falling SCLK edge after

goes low, all on-chip circuitry starts to power up. It takes

approximately 5 μs for the AD7887 internal circuitry to be fully

powered up. As a result, a conversion (or sample-and-hold

acquisition) should not be initiated during this 5 μs. The input

signal is sampled on the second rising edge of SCLK following

the

falling edge. The user should ensure that 5 μs elapses

between the first falling edge of

SCLK

and the second rising

edge of SCLK after the

falling edge, as shown in Figure 18.

In microcontroller applications (or with a slow serial clock), this

is readily achievable by driving the

input from one of the

port lines and ensuring that the serial data read (from the

microcontroller’s serial port) is not initiated for 5 μs. However,

for higher speed serial clocks, it will not be possible to have a

5 μs delay between powering up and the first rising edge of the

SCLK. Therefore, the user must write to the control register to

exit this mode and (by writing PM1 = 0 and PM0 = 1) put the

part into Mode 2. A second conversion needs to be initiated

when the part is powered up to get a conversion result, as

shown in Figure 19. The write operation that takes place in

conjunction with this second conversion can put the part back

into Mode 3, and the part goes into power-down mode when

the conversion sequence ends.

Mode 4 (PM1 = 1, PM0 = 1)

In this mode, the AD7887 automatically enters a standby (or

sleep) mode at the end of every conversion. In this standby

mode, all on-chip circuitry, apart from the on-chip reference, is

powered down. This mode is similar to Mode 3, but, in this

case, the power-up time is much shorter because the on-chip

reference remains powered up at all times.

Figure 20 shows the general diagram of the operation of the

AD7887 in this mode. On the first falling SCLK edge after

goes low, the AD7887 comes out of standby. The AD7887 wake-

up time is very short in this mode, so it is possible to wake up

the part and carry out a valid conversion in the same read/write

operation. The input signal is sampled on the second rising

edge of SCLK following the

falling edge. At the end of

conversion (last rising edge of SCLK), the part automatically

enters its standby mode.

Rev. E | Page 14 of 24

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD7887BR-REEL

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Analog to Digital Converters - ADC 2.7V-5.25V Micropwr 2-Ch 125kSPS 12-Bit

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