Data Sheet AD7887
SERIAL INTERFACE
Figure 21 shows the detailed timing diagrams for serial
interfacing to the AD7887. The serial clock provides the
conversion clock and also controls the transfer of information
to and from the AD7887 during conversion.
CS
initiates the data transfer and conversion process. For some
modes, the falling edge of
CS
wakes up the part. In all cases, it
gates the serial clock to the
AD7887 and puts the on-chip
track/hold into track mode. The input signal is sampled on the
second rising edge of the SCLK input after the falling edge of
CS
. Thus, the first one and one-half clock cycles after the falling
edge of
CS
are when the acquisition of the input signal takes
place. This time is denoted as the acquisition time (t
ACQ
). In
modes where the falling edge of
CS
wakes up the part, the
acquisition time must allow for the wake-up time of 5 μs. The
on-chip track/hold goes from track mode to hold mode on the
second rising edge of SCLK, and a conversion is also initiated
on this edge. The conversion process takes an additional
fourteen and one-half SCLK cycles to complete. The rising edge
of
CS
puts the bus back into three-state. If
CS
is left low, a new
conversion can be initiated.
In dual-channel operation, the input channel that is sampled is
the one that was selected in the previous write to the control
register. Thus, in dual-channel operation, the user must write
the channel address for the next conversion while the present
conversion is in progress.
Writing of information to the control register takes place on the
first eight rising edges of SCLK in a data transfer. The control
register is always written to when a data transfer takes place.
However, the AD7887 can be operated in a read-only mode by
tying DIN low, thereby loading all 0s to the control register
every time. When operating the AD7887 in write/read mode,
the user must be careful to always set up the correct
information on the DIN line when reading data from the part.
Sixteen serial clock cycles are required to perform the con-
version process and to access data from the AD7887. In
applications where the first serial clock edge following
CS
going
low is a falling edge, this edge clocks out the first leading zero.
Thus, the first rising clock edge on the SCLK clock has the first
leading zero provided. In applications where the first serial
clock edge following
CS
going low is a rising edge, the first
leading zero may not be set up in time for the processor to read
it correctly. However, subsequent bits are clocked out on the
falling edge of SCLK so that they are provided to the processor
on the following rising edge. Thus, the second leading zero is
clocked out on the falling edge subsequent to the first rising
edge. The final bit in the data transfer is valid on the 16
th
rising
edge, having been clocked out on the previous falling edge.
DONTC
ZERO
ZERO
0
MP1MPHCL
AUD
/NI
SFER
SCLK
651
15
DOUT
DIN
2
3 4
16
t
1
t
ACQ
t
CONVERT
t
2
t
6
t
7
t
3
t
8
DB11
DB0
DB10
DB9
THREE-
STATE
FOUR LEADING ZEROS
CS
THREE-
STATE
t
4
t
5
06191-021
Figure 21. Serial Interface Timing Diagram
Rev. E | Page 17 of 24
