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ADE7761BARSZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
ADE7761B
Rev. 0 | Page 15 of 24
)sin(2)(
0
h
h
h
O
thIIti β+ω××+=
∑
∞
≠
(2)
where:
i(t) is the instantaneous current.
I
O
is the dc component.
I
h
is the rms value of Current Harmonic h.
β
h
is the phase angle of the current harmonic.
Using Equation 1 and Equation 2, the Active Power P can be
expressed in terms of its fundamental active power (P
1
) and
harmonic active power (P
H
).
P = P
1
+ P
H
where:
P
1
= V
1
× I
1
cos(Φ
1
) (3)
Φ
1
= α
1
− β
1
and
)cos(
2
∑
∞
=
Φ××=
h
hhh
H
IVP
(4)
hhh
β
−α=Φ
As can be seen in Equation 4, a harmonic active power component
is generated for every harmonic provided that the harmonic is
present in both the voltage and current waveforms. The power
factor calculation was previously shown to be accurate in the
case of a pure sinusoid; therefore, the harmonic active power
must also correctly account for the power factor because it is
made up of a series of pure sinusoids.
Note that the input bandwidth of the analog inputs is 7 kHz
with an internal oscillator frequency of 450 kHz.
HPF and Offset Effects
Equation 5 shows the effect of offsets on the active power
calculation.
Figure 24 shows the effect of offsets on the active
power calculation in the frequency domain.
)cos()cos(
2
))cos(())cos((
)()(
tIVtIV
IV
IV
tIItVV
tItV
0110
11
10
1010
ω××+ω××+
×
+×
=ω×+×ω×+
=×
(5)
As shown in Equation 5 and
Figure 24, an offset on Channel V1
and Channel V2 contributes a dc component after multiplication.
Because this dc component is extracted by the LPF and used to
generate the active power information, the offsets contribute
a constant error to the active power calculation. This problem is
easily avoided in the ADE7761B with the HPF in Channel V1. By
removing the offset from at least one channel, no error component
can be generated at dc by the multiplication. Error terms at cos(ωt)
are removed by the LPF and the digital-to-frequency conversion
(see the
Digital-to-Frequency Conversion section).
The HPF in Channel V1 has an associated phase response that
is compensated for on-chip.
Figure 25 and Figure 26 show the
phase error between channels with the compensation network
activated. The ADE7761B is phase compensated up to 1 kHz as
shown, which ensures a correct active harmonic power calculation
even at low power factors.
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR ACTIVE
POWER CALCULATION
2ω
FREQUENCY (Rad/s)
0ω
V
1
× I
0
V
0
× I
1
V
1
× I
1
2
06797-022
Figure 24. Effect of Channel Offsets on the Active Power Calculation
FREQUENCY (Hz)
0 100
PHASE (Degrees)
–0.05
–0.10
0
0.05
0.10
0.15
0.20
0.25
0.30
200 300 400 500 600 700 800 900 1000
06797-023
Figure 25. Phase Error Between Channels (0 Hz to 1 kHz)
FREQUENCY (Hz)
40
PHASE (Degrees)
–0.05
–0.10
0.05
0
0.10
0.15
0.20
0.25
0.30
45 50 55 60 65 70
06797-024
Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)
ADE7761B
Rev. 0 | Page 16 of 24
DIGITAL-TO-FREQUENCY CONVERSION
As described in the Active Power Calculation section, the digital
output of the low-pass filter after multiplication contains the
active power information. However, because this LPF is not an
ideal brick wall filter implementation, the output signal also
contains attenuated components at the line frequency and its
harmonics, that is, cos(hωt), where
h = 1, 2, 3, …, and so on.
The magnitude response of the filter is given by
2
)Hz5.4/(1
1
)(
f
fH
=
=
(6)
For a line frequency of 50 Hz, this gives an attenuation of the 2ω
(100 Hz) component of approximately −26.9 dB. The dominating
harmonic is at twice the line frequency, cos(2ωt), due to the
instantaneous power signal.
Figure 27 shows the instantaneous active power signal output of
the LPF, which still contains a significant amount of instantaneous
power information, cos(2ωt). This signal is then passed to the
digital-to-frequency converter, where it is integrated (accumulated)
over time to produce an output frequency. This accumulation of
the signal suppresses or averages out any non-dc components in
the instantaneous active power signal. The average value of a
sinusoidal signal is zero. Therefore, the frequency generated by
the ADE7761B is proportional to the average active power.
F
1
F
2
CF
DIGITAL-TO-
FREQUENCY
DIGITAL-TO-
FREQUENCY
MULTIPLIER
LPF
V
I
0 ω 2ω
FREQUENCY (Rad/s)
LPF TO EXTRACT
ACTIVE POWER
(DC TERM)
TIME
TIME
FREQUENCY FREQUENCY
F
1
CF
INSTANTANEOUS ACTIVE POWER SIGNAL (FREQUENCY DOMAIN)
0
6797-025
Figure 27. Active Power to Frequency Conversion
Figure 27 also shows the digital-to-frequency conversion for
steady load conditions: constant voltage and current. As can be
seen in
Figure 27, the frequency output CF varies over time,
even under steady load conditions. This frequency variation is
primarily due to the cos(2ωt) component in the instantaneous
active power signal.
The output frequency on CF can be up to 2048 times higher
than the frequency on F1 and F2. This higher output frequency
is generated by accumulating the instantaneous active power
signal over a much shorter time while converting it to a frequency.
This shorter accumulation period means less averaging of the
cos(2ωt) component. As a consequence, some of this instantaneous
power signal passes through the digital-to-frequency conversion.
This is not a problem in the application.
Where CF is used for calibration purposes, the frequency should
be averaged by the frequency counter, which removes any ripple.
If CF is being used to measure energy, such as in a microprocessor-
based application, the CF output should also be averaged to calcu-
late power. Because the F1 and F2 outputs operate at a much
lower frequency, much more averaging of the instantaneous active
power signal is carried out. The result is a greatly attenuated
sinusoidal content and a virtually ripple-free frequency output.
TRANSFER FUNCTION
Frequency Output F1 and Frequency Output F2
The ADE7761B calculates the product of two voltage signals
(on Channel V1 and Channel V2) and then low-pass filters this
product to extract active power information. This active power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active high
pulses. The pulse rate at these outputs is relatively low, for
example, 0.37 Hz maximum for ac signals with S0 = S1 = 0
(see
Table 8). This means that the frequency at these outputs
is generated from active power information accumulated over
a relatively long period. The result is an output frequency that
is proportional to the average active power. The averaging of the
active power signal is implicit to the digital-to-frequency conver-
sion. The output frequency or pulse rate is related to the input
voltage signals by
2
21
13.6
,
REF
41rmsrms
V
fV2V1Gain
FrequencyFF
−
×
××
×
=
(7)
where:
F
1
, F
2
Frequency is the output frequency on F1 and F2 (Hz).
V1
rms
is the differential rms voltage signal on Channel V1 (V).
V2
rms
is the differential rms voltage signal on Channel V2 (V).
Gain is 1 or 16, depending on the PGA gain selection made
using Logic Input PGA.
V
REF
is the reference voltage (2.5 V ± 8%) (V).
f
1–4
is one of four possible frequencies selected by using Logic
Input S0 and Logic Input S1 (see
Table 6).
ADE7761B
Rev. 0 | Page 17 of 24
Table 6. f
1–4
Frequency Selection
S1 S0 f
1–4
(Hz)
1
f
1−4
= OSC/2
n2
0 0 1.72 OSC/2
18
0 1 3.44 OSC/2
17
1 0 6.86 OSC/2
16
1 1 13.7 OSC/2
15
1
Values are generated using the nominal frequency of 450 kHz.
2
f
1–4
are a binary fraction of the master clock and, therefore, vary with the
internal oscillator frequency (OSC).
Frequency Output CF
The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the f
1–4
frequency selected, the higher the CF scaling.
Table 7 shows
how the two frequencies are related, depending on the states of
Logic Input S0, Logic Input S1, and Logic Input SCF. Because of
its relatively high pulse rate, the frequency at this logic output is
proportional to the instantaneous active power. As with F
1
and
F
2
, the frequency is derived from the output of the low-pass filter
after multiplication. However, because the output frequency is high,
this active power information is accumulated over a much shorter
time. Therefore, less averaging is carried out in the digital-to-
frequency conversion. With much less averaging of the active
power signal, the CF output is much more responsive to power
fluctuations (see
Figure 22).
Table 7. Relationship Between CF and F1, F2 Frequency
Outputs
SCF S1 S0 f
1–4
(Hz) CF Frequency Output
1 0 0 1.72 128 × F
1
, F
2
0 0 0 1.72 64 × F
1
, F
2
1 0 1 3.44 64 × F
1
, F
2
0 0 1 3.44 32 × F
1
, F
2
1 1 0 6.86 32 × F
1
, F
2
0 1 0 6.86 16 × F
1
, F
2
1 1 1 13.7 16 × F
1
, F
2
0 1 1 13.7 2048 × F
1
, F
2
Example
In this example, if ac voltages of ±660 mV peak are applied to
Channel V1 and Channel V2, the expected output frequency on
CF, F1, and F2 is calculated as
Gain = 1, PGA = 0
f
1–4
= 1.7 Hz, SCF = S1 = S0 = 0
V1
rms
= rms of 660 mV peak ac = 0.66/√2 V
V2
rms
= rms of 660 mV peak ac = 0.66/√2 V
V
REF
= 2.5 V (nominal reference value)
Note that if the on-chip reference is used, actual output
frequencies may vary from device to device due to a reference
tolerance of ±8%.
Hz367.0
5.222
Hz72.166.066.013.6
,
2
21
=
××
×
××
=FrequencyFF
CF Frequency = F
1
, F
2
× 64 = 23.5 Hz
As can be seen from these two example calculations, the maximum
output frequency for ac inputs is always half of that for dc input
signals.
Table 8 shows a complete listing of all maximum output
frequencies for ac signals.
Table 8. Maximum Output Frequencies on CF, F1, and F2 for
AC Inputs
SCF S1 S0
F
1
, F
2
Maximum
Frequency (Hz),
1/t
2
CF Maximum
Frequency (Hz),
1/t
5
CF-to-F
1
Ratio
1 0 0 0.37 46.98 128
0 0 0 0.37 23.49 64
1 0 1 0.73 46.98 64
0 0 1 0.73 23.49 32
1 1 0 1.47 46.98 32
0 1 0 1.47 23.49 16
1 1 1 2.94 46.98 16
0 1 1 2.94 6013 2048
FAULT DETECTION
The ADE7761B incorporates a novel fault detection scheme
that warns of fault conditions and allows the ADE7761B to
continue accurate billing during a fault event. The ADE7761B
does this by continuously monitoring both the phase and neutral
(return) currents. A fault is indicated when these currents differ
by more than 6.25%. However, even during a fault, the output
pulse rate on F1 and F2 is generated using the larger of the two
currents. Because the ADE7761B looks for a difference between
the voltage signals on V
1A
and V
1B
, it is important that both
current transducers be closely matched.
On power-up, the output pulse rate of the ADE7761B is propor-
tional to the product of the voltage signals on V
1A
and Channel V2.
If the difference between V
1A
and V
1B
on power-up is greater than
6.25%, the fault indicator (FAULT) becomes active after about
1 second. In addition, if V
1B
is greater than V
1A
, the ADE7761B
selects V
1B
as the input. Fault detection is automatically disabled
when the voltage signal on Channel V1 is less than 0.3% of the
full-scale input range. This eliminates false detection of a fault
due to noise at light loads.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADE7761BARSZ

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Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized Energy Metering IC w/ On-Chip Fault
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