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MF0MOU2001DA4,118

P1-P3P4-P6P7-P9P10-P12P13-P15
MF0ICU2_SDS_32 © NXP B.V. 2009. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3 — 19 May 2009
171432 7 of 15
NXP Semiconductors
MF0ICU2
MIFARE Ultralight C
7.3.2 Lock bytes
Lock bytes enable the user to lock parts of the complete memory area for writing. A Read
from user memory area cannot be restricted via lock bytes functionality. For this, please
refer to the authentication functionality, (see Section 7.3.4 “3DES Authentication”).
7.3.3 OTP bytes
OPT bytes are pre-set to all “0” after production. These bytes may be bit-wise modified by
a WRITE command.
7.3.4 3DES Authentication
3DES Authentication proves that two entities have the same secret and each entity can be
seen as a reliable partner for the coming communication. The applied encryption
algorithm ek() is 2 key 3DES encryption (see Ref. 9 “NIST SP800-67: Recommendation
for the Triple Data Encryption Algorithm (TDEA) Block Cipher, Version 1.1 May 19, 2008”)
in Cipher-Block Chaining (CBC) mode as described in ISO/IEC 10116 (see Ref. 10
“ISO/IEC 10116: Information technology - Security techniques - Modes of operation for an
n-bit block cipher, February 1, 2006”).
7.3.5 Data pages
MF0ICU2 features 144 bytes of data memory. The address range from page 04h to 27h
constitutes the read/write area.
A write access to data memory is achieved with WRITE (see Section 7.5.7 “WRITE”) or
COMPATIBILITY WRITE (see Section 7.5.8 “COMPATIBILITY WRITE”) command. In both
cases, 4 bytes of memory - (one page) - will be overwritten. Write access to data memory
can be permanently restricted via lock bytes (see Section 7.3.2 “Lock bytes”) and/or
permanently or temporary restricted using an authentication (see Section 7.3.4 “3DES
Authentication”).
NFC Forum Type 2 Tag compliancy
MF0ICU2 has been designed to be compliant with NFC Forum Type 2 Tag specification
(see Ref. 5 “MIFARE Ultralight as Type 2 Tag”). With its 144 bytes of data memory, it can
easily support use cases like Smart Poster, Hand over, SMS, URL or Call Request.
7.4 Counter
MF0ICU2 features 16-bit one way counter. In its delivery state, counter value is set to
0000h.
MF0ICU2_SDS_32 © NXP B.V. 2009. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3 — 19 May 2009
171432 8 of 15
NXP Semiconductors
MF0ICU2
MIFARE Ultralight C
7.5 Command set
The ATQA and SAK are identical as for MF0ICU1 (see Ref. 7 “MF0ICU1 Functional
specification MIFARE Ultralight”). For information on ISO 14443 card activation, see Ref.
3 “MIFARE ISO/IEC 14443 PICC Selection”.
The MF0ICU2 comprises the following command set:
7.5.1 REQA
The MF0ICU2 accepts the REQA command in Idle state only. The response is the 2-byte
ATQA. REQA and ATQA are implemented fully according to ISO/IEC14443-3.
7.5.2 WUPA
The MF0ICU2 accepts the WUPA command in the Idle and Halt state only. The response
is the 2-byte ATQA. WUPA is implemented fully according to ISO/IEC14443-3.
7.5.3 ANTICOLLISION and SELECT of cascade level 1
The ANTICOLLISION and SELECT commands are based on the same command code.
They differ only in the Parameter byte. This byte is per definition 70h in case of SELECT.
The MF0ICU2 accepts these commands in the Ready1 state only. The response is part 1
of the UID.
7.5.4 ANTICOLLISION and SELECT of cascade level 2
The ANTICOLLISION and SELECT commands are based on the same command code.
They differ only in the parameter byte. This byte is per definition 70h in case of SELECT.
The MF0ICU2 accepts these commands in the Ready2 state only. The response is part 2
of the UID.
7.5.5 READ
The READ command needs the page address as a parameter. Only addresses 00h to
2Bh are decoded. For higher addresses the MF0ICU2 returns a NAK. The MF0ICU2
responds to the READ command by sending 16 bytes starting from the page address
defined in the command (e.g. if ADR is ‘03h‘ pages 03h, 04h, 05h, 06h are returned). If
ADR is ‘2Bh’, the contents of pages 2Bh, 00h, 01h and 02h is returned). This is also
applied by configuring the authentication address.
7.5.6 HALT
The HALT command is used to set already processed MF0ICU2 devices into a different
waiting state (Halt instead of Idle), which allows a simple separation between devices
whose UIDs are already known (as they have already passed the anticollision procedure)
and devices that have not yet been identified by their UIDs.
7.5.7 WRITE
The WRITE command is used to program the lock bytes in page 02h, the OTP bytes in
page 03h or the data bytes in pages 04h to 05h. A WRITE command is performed
page-wise, programming 4 bytes in a page.
MF0ICU2_SDS_32 © NXP B.V. 2009. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3 — 19 May 2009
171432 9 of 15
NXP Semiconductors
MF0ICU2
MIFARE Ultralight C
7.5.8 COMPATIBILITY WRITE
The COMPATIBILITY WRITE command was implemented to accommodate the
established MIFARE PCD infrastructure. Even though 16 bytes are transferred to the
MF0ICU2, only the least significant 4 bytes (bytes 0 to 3) will be written to the specified
address. It is recommended to set the remaining bytes 4 to 15 to all ‘0’.
7.5.9 AUTHENTICATE
The authentication is performed in two steps, therefore MF0ICU2 command set supports
two AUTHENTICATE commands.
The commands are performed in the same protocol as READ, WRITE and
COMPATIBILITY WRITE.
8. Limiting values
[1] Stresses above one or more of the limiting values may cause permanent damage to the device.
[2] Exposure to limiting values for extended periods may affect device reliability.
[3] MIL Standard 883-C method 3015; Human body model: C = 100 pF, R = 1.5 kΩ.
Table 4. Limiting values
[1][2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
I
I
input current - 30 mA
T
stg
storage temperature −55 +125 °C
T
amb
ambient temperature −25 +70 °C
V
ESD
electrostatic discharge
voltage
measured on pin
LA-LB
[3]
2-kV
P1-P3P4-P6P7-P9P10-P12P13-P15

MF0MOU2001DA4,118

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Manufacturer:
NXP Semiconductors
Description:
RF Transceiver MIFARE Ultralight C PLLMC
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