MC100LVEL30DWR2G

© Semiconductor Components Industries, LLC, 2016
July, 2016 Rev. 8
1 Publication Order Number:
MC100LVEL30/D
MC100LVEL30
3.3 V ECL Triple D Flip‐Flop
with Set and Reset
Description
The MC100LVEL30 is a triple master-slave D flip-flop with
differential outputs. Data enters the master latch when the clock input
is LOW and transfers to the slave upon a positive transition on the
clock input.
In addition to a common Set input individual Reset inputs are
provided for each flip-flop. Both the Set and Reset inputs function
asynchronous and overriding with respect to the clock inputs.
Features
1200 MHz Minimum Toggle Frequency
450 ps Typical Propagation Delays
ESD Protection: > 2 kV Human Body Model
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= 3.0 V to 3.8 V
Internal Input 75 kW Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D
)
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 347 Devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
SOIC20 WB
DW SUFFIX
CASE 751D05
20
1
100LVEL30
AWLYYWWG
ORDERING INFORMATION
Device Package Shipping
MC100LVEL30DWG SOIC20 WB
(Pb-Free)
38 Units / Tube
MC100LVEL30DWR2G
1000 Tape & Reel
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
SOIC20 WB
(Pb-Free)
MC100LVEL30
www.onsemi.com
2
D1
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View)
R0 R1 D2
1718 16 15 14 13 12
43
56789
Q0
11
10
V
CC
Q1 Q1 V
CC
Q2 Q2 V
EE
D0
1920
21
V
CC
Q0
CLK0 CLK1S012 CLK2 R2
D
RS
Q
Q
D
RS
Q
Q
D
RS
Q
Q
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
R
L
L
H
L
H
Table 1. TRUTH TABLE
S
L
L
L
H
H
D
L
H
X
X
X
CLK
Z
Z
X
X
X
Q
L
H
L
H
Undef
Z = LOW to HIGH Transition
X = Don’t Care
Q
H
L
H
L
Undef
Table 2. PIN DESCRIPTION
FUNCTION
ECL Data Inputs
ECL Reset Inputs
ECL Clock Inputs
ECL Common Set Input
ECL Differential Data Outputs
Positive Supply
Negative Supply
PIN
D0D2
R0R2
CLK0CLK2
S012
Q0Q2; Q0Q2
V
CC
V
EE
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V 8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6 to 0
6 to 0
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC20 WB
SOIC20 WB
90
60
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 °C/W
T
sol
Wave Solder < 2 to 3 sec @ 248°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
MC100LVEL30
www.onsemi.com
3
Table 4. LVPECL DC CHARACTERISTICS (V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1))
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 55 62 55 62 55 64 mA
V
OH
Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage 1490 1825 1490 1825 1490 1825 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
2.0 V.
Table 5. LVNECL DC CHARACTERISTICS (V
CC
= 0.0 V; V
EE
= 3.3 V (Note 1))
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 55 62 55 62 55 64 mA
V
OH
Output HIGH Voltage (Note 2) 1085 1005 880 1025 955 880 1025 955 880 mV
V
OL
Output LOW Voltage (Note 2) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mV
V
IH
Input HIGH Voltage 1165 880 1165 880 1165 880 mV
V
IL
Input LOW Voltage 1810 1475 1810 1475 1810 1475 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
2.0 V.

MC100LVEL30DWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 3.3V/5V ECL Triple D-Type
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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