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DG4052EEN-T1-GE4

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
DG4051E, DG4052E, DG4053E
www.vishay.com
Vishay Siliconix
S16-0623-Rev. A, 11-Apr-16
13
Document Number: 69685
For technical questions, contact: analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Fig. 3 - Break-Before-Make
Fig. 4 - Charge Injection
A
B
C
ENABLE
GND
V-
V+
V
O
50 Ω
300 Ω
35 pF
X
X0 - X7
DG4051E
A
B
ENABLE
GND
V-
V+
V
O
50 Ω
300 Ω
35 pF
X or Y
X0 - X3 or
Y0- Y3
DG4052E
A or B
or C
ENABLE
GND
V-
V+
V
O
50 Ω
300 Ω
35 pF
X or Y or Z
X0, X1 or Y0,
Y1 or Z0, Z1
DG4053E
0 V
V+
50 %
80 %
t
D
V
O
V
A,B,C
V
X0
or V
Y0
or V
Z0
V+
V+
V+
0 V
A
B
C
ENABLE
GND
V-
V+
V
O
1 nF
X or Y or Z
Xx or Yx or Zx
0 V
V+
V
O
V
ENABLE
R
g
Channel
Select
V
g
ON
OFF
OFF
ΔV
O
t
r
< 5 ns
t
f
< 5 ns
DG4051E, DG4052E, DG4053E
www.vishay.com
Vishay Siliconix
S16-0623-Rev. A, 11-Apr-16
14
Document Number: 69685
For technical questions, contact: analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Fig. 5 - Insertion Loss
Fig. 6 - Crosstalk
Fig. 7 - Off Isolation
Fig. 8 - Source, Drain Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?69685
.
A
B
C
ENABLE
GND
V-
V+
V
OUT
X or Y or Z
X0 or Y0 or Z0
V
g
R
g
= 50 Ω
50 Ω
V
IN
Network Analyzer
Insertion Loss = 20 log
V
OUT
V
IN
A
B
C
ENABLE
GND
V-
V+
V
OUT
X or Y or Z
X0 or Y0 or Z0
V
g
R
g
= 50 Ω
50 Ω
V
IN
Network Analyzer
Crosstalk = 20 log
V
OUT
V
IN
50 Ω
Xx or Yx or Zx
A
B
C
ENABLE
GND
V-
V+
V
OUT
X or Y or Z
X0 or Y0 or Z0
V
g
R
g
= 50 Ω
50 Ω
V
IN
Network Analyzer
Off Isolation = 20 log
V
OUT
V
IN
V+
A
B
C
ENABLE
GND
V-
V+
X or Y or Z
X0 or Y0 or Z0
|
to
|
Xx or Yx or Zx
Impedance
Analyzer
Channel
Select
Package Information
www.vishay.com
Vishay Siliconix
Revision: 09-May-16
1
Document Number: 64694
For technical questions, contact: analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Thin miniQFN16 Case Outline
Notes
(1)
Use millimeters as the primary measurement.
(2)
Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
(3)
N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively.
(4)
Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.
(5)
The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body.
(6)
Package warpage max. 0.05 mm.
DIMENSIONS
MILLIMETERS
(1)
INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0 - 0.05 0 - 0.002
A3 0.15 ref. 0.006 ref.
b 0.15 0.20 0.25 0.006 0.008 0.010
D 2.50 2.60 2.70 0.098 0.102 0.106
e 0.40 BSC 0.016 BSC
E1.70
1.80 1.90
0.067
0.071 0.075
L 0.35 0.40 0.45 0.014 0.016 0.018
L1 0.45 0.50 0.55 0.018 0.020 0.022
N
(3)
16 16
Nd
(3)
44
Ne
(3)
44
ECN: T16-0226-Rev. B, 09-May-16
DWG: 6023
0.10 C
0.10
A
A3
C
0.10 C
0.10 C
Side view
Top view Bottom view
C
A
B
13
12 11 10
D
E
9
8
7
6
5
8
7
6
5
13
14
15
16
L1
1234
Pin #1 identier
(5)
Seating
plane
Terminal tip
(4)
16 x b
0.10
0.05
C
C
M
M
AB
1211109
4
15 x L
321
e
14
15
16
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

DG4052EEN-T1-GE4

Mfr. #:
Buy DG4052EEN-T1-GE4
Manufacturer:
Vishay / Siliconix
Description:
Multiplexer Switch ICs Dual 4 Ch Multiplxr 3-16V <50pA 35ns
Lifecycle:
New from this manufacturer.
Delivery:
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