MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
3.3 VOLT FRAME RATE COMMUNICATIONS PLL 3
MK1574 REV F 111605
Pin Descriptions
External Components
The MK1574 requires a minimum number of external components for proper operation. An RC network (see the
section “Loop Bandwidth and Loop Filter Component Selection”) should be connected between CAP1 and CAP2 as
close tot he device as possible. Decoupling capacitors of 0.01µF should be connected between VDD and GND on
pins 2, 3, 5 and 7, as close to the device as possible. A series termination resistor of 33Ω may be used close to
each clock output pin to reduce reflections.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 ICLK Input Clock input. Connect to an 8 kHz clock input.
2 VDD Power Connect to 3.3 V.
3 VDD Power Connect to 3.3 V.
4 CAP1 Input Connect to a ceramic capacitor and a resistor in series between this pin and
CAP2. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
5 GND Power Connect to ground.
6 CAP2 Power Connect to a ceramic capacitor and a resistor in series between this pin and
CAP1. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
7 GND Power Connect to ground.
8 FS0 Input Frequency select 0. Determines CLK outputs per table above.
9 8KOUT Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock
input.
10 CLK1 Output Clock 1 determined by status of FS3:0 per table above.
11 CLK2 Output Clock 2 determined by status of FS3:0 per table above.
12 CLK3 Output Clock 3 determined by status of FS3:0 per table above.
13 FS1 Input Frequency select 1. Determines CLK outputs per table above.
14 FS2 Input Frequency select 2. Determines CLK outputs per table above.
15 NC — No connect. Do not connect anything to this pin.
16 FS3 Input Frequency select 3. Determines CLK outputs per table above.
