MK1574-01SITR

MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
3.3 VOLT FRAME RATE COMMUNICATIONS PLL 4
MK1574 REV F 111605
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1574. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD = 3.3 V, Ambient temperature 0 to +70°C, unless stated otherwise
Item Rating
Supply Voltage, VDD (referenced to GND) -0.5 V to 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial) 0 to +70°C
Ambient Operating Temperature (industrial) -40 to +85°C
Storage Temperature -65 to +150°C
Junction Temperature 150°C
Soldering Temperature 260°C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature (commercial) 0 +70 °C
Ambient Operating Temperature (industrial) -40 +85 °C
Power Supply Voltage (measured in respect to GND) +3.13 +5.5 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.0 3.6 V
Input High Voltage V
IH
2V
Input Low Voltage V
IL
0.8 V
Output High Voltage V
OH
I
OH
= -4 mA VDD-0.4 V
Output High Voltage V
OH
I
OH
= -25 mA 2.4 V
Output Low Voltage V
OL
I
OL
= 25 mA 0.4 V
Operating Supply
Current
IDD No Load 13 mA
Short Circuit Current I
OS
Each output ±100 mA
Input Capacitance C
IN
7pF
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
3.3 VOLT FRAME RATE COMMUNICATIONS PLL 5
MK1574 REV F 111605
AC Electrical Characteristics
VDD = 3.3 V, Ambient Temperature 0 to +70°C, unless stated otherwise
Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
Thermal Characteristics
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of
the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is
recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or
NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric
properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is
converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are
calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set
by the capacitor C and the constant K1 using the formula:
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency f
IN
8.000 kHz
Output Clock Rise Time t
OR
0.8 to 2.0 V 1.5 ns
Output Clock Fall Time t
OF
2.0 to 0.8 V 1.5 ns
Output Clock Duty Cycle,
High time
t
DC
At VDD/2 40 49 to 51 60 %
Absolute Clock Period
Jitter
1ns
Actual Mean Frequency
Error Versus Target (note
1)
Any clock selection 0 0 ppm
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
JA
Still air 120 °C/W
θ
JA
1 m/s air flow 115 °C/W
θ
JA
3 m/s air flow 105 °C/W
Thermal Resistance Junction to Case θ
JC
58 °C/W
BW (Hz) =
C
K1
Equation 1
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL CLOCK SYNTHESIZER
IDT™ / ICS™
3.3 VOLT FRAME RATE COMMUNICATIONS PLL 6
MK1574 REV F 111605
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page 7)
shows the constants K1 = 0.0516 and K2 = 6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using equation 1,
Therefore,
3. A good value for the damping factor ζ is 0.707. From equation 2,
R =
Equation 2; ζ (zeta) is the damping factor
C
ζ * K2
C
K1
400 =
C
K1
C =
400
0.0516
(
)
2
= 16.6 nF (16 nF nearest standard value
R =
= 34.7 k (36 k nearest standard value)
16E-9
0.707 * 6.2

MK1574-01SITR

Mfr. #:
Manufacturer:
Description:
IC PLL FRAME RATE COMM 16-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union