MMA8491QR1 Datasheet MMA8491QT, MMA8491QR1 | P16-P18

MMA8491Q

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16 Freescale Semiconductor, Inc.

5 Register Descriptions

5.1 Register address map

5.2 Register bit map

Table 10. Register address map

(1)(2)

1. Register contents are preserved when EN pin is set high after sampling.

2. Register contents are reset when EN pin is set low.

Name Type Register Address

Auto-Increment Address

(3)

3. Auto-increment is the I

C feature that the I

C read address is automatically updated after each read. Auto-increment addresses which are not

a simple increment are highlighted in bold. The auto-increment addressing is only enabled when device registers are read using I

C burst

read mode. Therefore the internal storage of the auto-increment address is cleared whenever a stop-bit is detected.

Default Comment

STATUS

R 0x00 0x01 0x00

Read time status

OUT_X_MSB

R 0x01 0x02 Output

[7:0] are 8 MSBs of the 14-bit sample

OUT_X_LSB

R 0x02 0x03 Output

[7:2] are the 6 LSB of 14-bit sample

OUT_Y_MSB

R 0x03 0x04 Output

[7:0] are 8 MSBs of the 14-bit sample

OUT_Y_LSB

R 0x04 0x05 Output

[7:2] are the 6 LSB of 14-bit sample

OUT_Z_MSB

R 0x05 0x06 Output

[7:0] are 8 MSBs of the 14-bit sample

OUT_Z_LSB

R 0x06 0x00 Output

[7:2] are the 6 LSB of 14-bit sample

Table 11. Register bit map

Address Offset Name 7 6 5 4 3 2 1 0

0x00 STATUS R 0 0 0 0 ZYXDR ZDR YDR XDR

0x01 OUT_X_MSB R XD[13:6]

0x02 OUT_X_LSB R XD[5:0] 0 0

0x03 OUT_Y_MSB R YD[13:6]

0x04 OUT_Y_LSB R YD[5:0] 0 0

0x05 OUT_Z_MSB R ZD[13:6]

0x06 OUT_Z_LSB R ZD[5:0] 0 0

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5.3 Data registers

5.3.1 0x00 Status register

Register 0x00 reflects the real-time status information of the X, Y, and Z sample data. The data read bits (ZYXDR, ZDR, YDR,

XDR) are set when samples are taken and ready to be read.

Table 12. STATUS register

Field Description

ZYXDR

X, Y, Z-axis new Data Ready (and available)

•ZYXDR signals that a new sample for all channels is available.

• ZYXDR is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all channels

are read.

0: No new set of data ready (default value)

1: A new set of data is ready

ZDR

Z-axis new Data Ready (and available)

•ZDR is set whenever a new acceleration sample related to the Z-axis is generated.

• ZDR is cleared anytime OUT_Z_MSB register is read.

0: No new Z-axis data is ready (default value)

1: A new Z-axis data is ready

YDR

Y-axis new Data Ready (and available)

•YDR is set whenever a new acceleration sample related to the Y-axis is generated.

• YDR is cleared anytime OUT_Y_MSB register is read.

0: No new Y-axis data ready (default value)

1: A new Y-axis data is ready

XDR

X-axis new Data Ready (and available)

•XDR is set whenever a new acceleration sample related to the X-axis is generated.

• XDR is cleared anytime OUT_X_MSB register is read.

0: No new X-axis data ready (default value)

1: A new X-axis data is ready

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18 Freescale Semiconductor, Inc.

5.3.2 Accelerometer data registers (0x01–0x06)

These registers contain the X-axis, Y-axis, and Z-axis14-bit output sample data (expressed as 2's complement numbers).

• OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the auto-

incrementing address range of 0x01 – 0x06.

• The LSB registers can only be read immediately following the read access of the corresponding MSB register.

A random read access to the LSB registers is not possible.

• Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong to the same

data sample, even if a new data sample arrives between reading the MSB and the LSB byte.

• The accelerometer data registers should be read only after the status register has confirmed that new data on all axes is

available.

5.4 Accelerometer output conversion

Table 13. OUT_X_MSB: X_MSB register (0x01, Read-only)