CPC75282KATR Datasheet CPC75282KA, CPC75282KATR | P13-P15

PRELIMINARY

NTEGRATED

IRCUITS

IVISION

CPC75282

R00E PRELIMINARY 13

2.3 Switch Logic

2.3.1 Start-up

The CPC75282 uses smart logic to monitor the V

supply. Any time the V

is below an internally set

threshold, the smart logic places the control logic to

the all-off state until the LATCH

input is pulled low.

Prior to the assertion of a logic low at the LATCH

pin,

the switch control inputs must be properly conditioned.

2.3.2 Switch Timing

When switching from the ringing state to the idle/talk

state, the CPC75282 provides the ability to control the

release timing of the ringing switches, SW3 and SW4,

relative to the state of the switches, SW1 and SW2,

using simple logic inputs. The two available

techniques are referred to as make-before-break and

break-before-make operation. When the break switch

contacts of SW1 and SW2 are closed (made) before

the ringing switch contacts of SW3 and SW4 are

opened (broken), this is referred to as

make-before-break operation. Break-before-make

operation occurs when the ringing contacts of SW3

and SW4 are opened (broken) before the switch

contacts of SW1 and SW2 are closed (made).

With the CPC75282, make-before-break and

break-before-make operations can easily be

accomplished by applying the proper sequence of

logic-level inputs to the device.

The logic sequences for either mode of operation are

given in “Make-Before-Break Operation Logic

Table (Ringing to Talk Transition)” on page 13 and

“Break-Before-Make Ringing to Talk Transition

Logic Sequence CPC7592xA/B” on page 14. Logic

states and explanations are shown in “Truth Tables”

on page 11.

2.3.3 Make-Before-Break Operation

To use make-before-break operation, change the logic

inputs from the ringing state directly to the idle/talk

state. Application of the idle/talk state opens the

ringing return switch, SW3, as the break switches,

SW1 and SW2, close. The ringing switch, SW4,

remains closed until the next zero-crossing of the

ringing current. While in the make-before-break state,

ringing potentials in excess of the CPC75282

protection circuitry thresholds will be diverted away

from the SLIC.

2.3.4: Make-Before-Break Operation Logic Table (Ringing to Talk Transition)

State

(CFG=0, P3=0)

P2 P1

LATCH

OFF

Timing

Break

Switches

& 2

Ringing

Return

Switch

Ringing

Switch

Test

Switches

& 6

Ringing 1 0

-OffOn On Off

Make-

before-

break

SW4 waiting for next zero-current

crossing to turn off. Maximum time is

one-half of the ringing cycle. In this

transition state current limited by the DC

break switch current limit value will be

sourced from the ring node of the SLIC.

On Off On Off

Idle/Talk 0 0 Zero-cross current has occurred

On Off Off Off

PRELIMINARY

NTEGRATED

IRCUITS

IVISION

CPC75282

14 PRELIMINARY R00E

Break-before-make operation occurs when the ringing

switches open before the break switches, SW1 and

SW2, close.

2.3.5: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B

2.3.6 Break -Before- Make Operation

Break-before-make operation can be achieved using

OFF

to disable all of the switches when pulled to a

logic low. Although logically disabled, an active

(closed) ringing switch, SW4, will remain closed until

the next zero crossing current event.

1. Pull OFF

to a logic low to end the ringing state.

This opens the ringing return switch, SW3, and

prevents any other switches from closing.

2. Keep OFF

low for at least one-half the duration

of the ringing cycle period to allow sufficient time

for a zero crossing current event to occur and for

the circuit to enter the break-before-make state.

3. During the OFF

low period, set the P1, P2, and

P3 inputs to the idle/talk state.

4. Release OFF

, allowing the internal pull-up to

activate the break switches.

2.4 Data Latch

The CPC75282 has integrated transparent data

latches. The latch enable operation is controlled by

logic input levels at the LATCH

pin. Data input to the

latch is via the input pins P1, P2, and P3 while the

outputs of the data latch are internal nodes used for

state control. When the latch enable control pin is at a

logic 0 the data latch is transparent and the input

control signals flow directly through the data latch to

the state control circuitry. A change in input will be

reflected by a change in the switch states.

Whenever the latch enable control pin is at logic 1, the

data latch is active and data is locked. Subsequent

changes to the input controls P1, P2, and P3 will not

result in a change to the control logic or affect the

existing switch states.

The switches will remain in the state they were in

when the LATCH

changes from logic 0 to logic 1, and

will not respond to changes in input as long as the

LATCH

is at logic 1. However, neither the T

SDx

nor

the OFF

are affected by the latch function. Since

internal thermal shutdown control and external OFF

control is not affected by the state of the latch enable

input, T

SDx

and OFF

will override state control.

2.5 T

Pin Description

The T

SDx

pins are bidirectional I/O structures with

internal pull-up resistors sourced from V

. As

outputs, these pins indicate the status of the thermal

shutdown circuitry for the associated channels.

Typically, during normal operation, these pins will be

pulled up to V

, but, under fault conditions that

create excess thermal loading, the channels will enter

thermal shutdown and a logic low will be output.

As inputs, the T

SDx

pins are utilized to place the

channel into the All-Off state by simply pulling the

input low. For applications using low-voltage logic

devices (lower than V

), IXYS Integrated Circuits

Division recommends the use of an open-collector or

an open-drain type output to control T

SDx

. This avoids

State

CFG=0, P3=0

P2 P1

LATCH

OFF

Timing

Break

Switches

& 2

Ringing

Return

Switch

Ringing

Switch

Test

Switches

& 6

Ringing 1 0

1-OffOn On Off

All-Off 1 1 0

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero

current to turn off.

Off Off

On Off

All-Off 1 1 0

Zero current has occurred.

SW4 has opened

Off Off Off Off

Talk 0 0 1 Break switches close.

On Off Off Off

PRELIMINARY

NTEGRATED

IRCUITS

IVISION

CPC75282

R00E PRELIMINARY 15

sinking the T

SDx

pull up bias current to ground during

normal operation when the All-Off state is not

required. If T

SDx

is set to a logic 1 or tied to V

, the

channel just ignores this input, and still enters the

thermal shutdown state at high temperature.

2.6 Ringing Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off,

the ringing switch is designed to delay the change in

state until the next zero-crossing. Once on, the switch

requires a zero-current cross to turn off, and therefore

should not be used to switch a pure DC signal. The

switch will remain in the on state no matter the logic

input until the next zero crossing. These switching

characteristics will reduce and possibly eliminate

overall system impulse noise normally associated with

ringing switches. See IXYS Integrated Circuits

Division’s application note, AN-144, Impulse Noise

Benefits of Line Card Access Switches, for more

information. The attributes of ringing switch, SW4,

may make it possible to eliminate the need for a

zero-cross switching scheme. A minimum impedance

of 300: in series with the ringing generator is

recommended.

2.7 Power Supplies

Both a +5V supply and battery voltage are connected

to the CPC75282. Switch state control is powered

exclusively by the +5V supply. As a result, the

CPC75282 exhibits extremely low power consumption

during active and idle states. Although battery power

is not used for switch control, it is required to supply

current during negative overvoltage fault conditions at

tip and ring.

2.8 Battery Voltage Monitor

The CPC75282 also uses the V

BAT

voltage to monitor

battery voltage. If system battery voltage is lost, both

channels of the CPC75282 immediately enter the

All-Off state. It remains in this state until the battery

voltage is restored. The device also enters the All-Off

state if the battery voltage rises more positive than

about –10V with respect to ground and remains in the

All-Off state until the battery voltage drops below

approximately –15V with respect to ground. This

battery monitor feature draws a small current from the

battery (less than 1PA typical) and will add slightly to

the device’s overall power dissipation.

2.9 Protection

2.9.1 Diode Bridge

Both channels of the CPC75282 use a combination of

current limited break switches, a diode bridge, and a

thermal shutdown mechanism to protect the SLIC

device or other associated circuitry from damage

during line transient events, such as lightning. During

a positive transient condition, the fault current is

conducted through the diode bridge to ground via

GND

. Voltage is clamped to a diode drop above

ground. Negative lightning is directed to battery via

steering diodes in the diode bridge. For power

induction or power-cross fault conditions, the positive

cycle of the transient is clamped to a diode drop above

ground and the fault current directed to ground. The

negative cycle of the transient is steered to battery.

Fault currents are limited by the current-limit circuit.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device is

in the Idle/Talk state, the current is passed along the

line to the integrated protection circuitry, and restricted

by the dynamic current limit response of the active

switches. During the Idle/Talk state, when a 1000V

10x1000Ps lightning pulse (GR-1089-CORE

lightning) is applied to the line though a properly

clamped external protector, the current seen at T

LINE

and R

LINE

will be a pulse with a typical magnitude of

2.5A and a duration less than 0.5Ps.

If a power-cross fault occurs with the device in the

Idle/Talk state, the current is passed though break

switches, SW1 and SW2, on to the integrated

protection circuit, but is limited by the DC current limit

response of the two break switches. The DC current

limit is dependent on the switch differential voltage, as

shown in “Figure 2: Switches 1-3” on page 17.

Note that the current limit circuitry has a negative

temperature coefficient. As a result, if the device is

subjected to extended heating due to a power cross

fault condition, the measured current at T

LINE

and

LINE

will decrease as the device temperature

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CPC75282KATR

Mfr. #:

Buy CPC75282KATR

Manufacturer:

IXYS Integrated Circuits

Description:

Switch ICs - Various 6-pole SOIC LCAS

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

CPC75282KATR

CPC75282KATR

Products related to this Datasheet