ICS854S202AYI-01 REV. A DECEMBER 18, 2012 13 ©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S202I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S202I-01 is the sum of the core power plus the output power dissipated due to the load.
The following is the power dissipation for V
DD
= 2.5V + 5% = 2.625V, which gives worst case results.
•Power
MAX
= V
DD_MAX
* I
DD_MAX
= 2.6255V * 128mA = 336mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature
at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = T
JA
* Pd_total + T
A
Tj = Junction Temperature
T
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance T
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 70.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.336W * 70.2°C/W = 108.6°C. This is
below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance T
JA
for 48 Lead LQFP, Forced Convection
T
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 70.2°C/W 60.4°C/W 56.9°C/W
