ICS854S202AYI-01 REV. A DECEMBER 18, 2012 2 ©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number Name Type Description
1 CLK2 Input Pulldown Non-inverting differential clock input.
2 nCLK2 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
3,
4,
9,
10
SELA_0,
SELA_1,
SELA_2,
SELA_3
Input Pulldown
Clock select pins for Bank A output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3B.
5, 18, 32, 43 V
DD
Power Power supply pins.
6, 7 QA, nQA Output Clock outputs. LVDS interface levels.
8, 15, 22, 29,
39, 46
GND Power Power supply ground.
11 CLK3 Input Pulldown Non-inverting differential clock input.
12 nCLK3 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
13 nCLK4 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
14 CLK4 Input Pulldown Non-inverting differential clock input.
16 nCLK5 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
17 CLK5 Input Pulldown Non-inverting differential clock input.
18, 43 V
DD
Power Positive supply pins.
19 OEA Input Pullup
Output enable pin. Controls enabling and disabling of QA, nQA
output pair. LVCMOS/LVTTL interface levels.
20 CLK6 Input Pulldown Non-inverting differential clock input.
21 nCLK6 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
23 CLK7 Input Pulldown Non-inverting differential clock input.
24 nCLK7 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
25 nCLK8 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
26 CLK8 Input Pulldown Non-inverting differential clock input.
27,
28,
33,
34
SELB_3,
SELB_2,
SELB_1,
SELB_0
Input Pulldown
Clock select pins for Bank B output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3C.
30, 31 nQB, QB Output Clock outputs. LVDS interface levels.
35 nCLK9 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
36 CLK9 Input Pulldown Non-inverting differential clock input.
37 nCLK10 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
38 CLK10 Input Pulldown Non-inverting differential clock input.
40 nCLK11 Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
41 CLK11 Input Pulldown Non-inverting differential clock input.
42 OEB Input Pullup
Output enable pin. Controls enabling and disabling of QB, nQB
output pair. LVCMOS/LVTTL interface levels.
44 CLK0 Input Pulldown Non-inverting differential clock input.
