ICS854S202AYI-01 REV. A DECEMBER 18, 2012 7 ©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and
is most often the specified plot in many applications. Phase noise is
defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset From Carrier Frequency (Hz)
SSB PHASE NOISE dBc/HZ
As with most timing specifications, phase noise measurements have
issues. The primary issue relates to the limitations of the equipment.
Often the noise floor of the equipment is higher than the noise floor
of the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Used the Rhode & Schwartz SMA100 as the input source.
ICS854S202AYI-01 REV. A DECEMBER 18, 2012 8 ©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information
2.5V Output Load Test Circuit
Part-to-Part Skew
Output Skew
Differential Input Level
Input Skew
SCOPE
Qx
nQx
2.5V±5%
POWER SUPPLY
+–
Float GND
V
DD
tsk(pp)
Part 1
Part 2
Qy
nQy
Qx
nQx
tsk(o)
Qy
nQy
Qx
nQx
V
CMR
Cross Points
V
PP
V
DD
nCLK[0:11]
CLK[0:11]
GND
nCLKy
CLKy
nQA
QA
nCLKx
CLKx
nQB
QB
ICS854S202AYI-01 REV. A DECEMBER 18, 2012 9 ©2012 Integrated Device Technology, Inc.
ICS854S202I-01 Data Sheet 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information, continued
Output Duty Cycle/Pulse Width
Propagation Delay
Differential Output Voltage Setup
Output Rise/Fall Time
MUX Isolation
Offset Voltage Setup
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
QA, QB
nQA, nQB
tp
LH
tp
HL
nCLK[0:11]
CLK[0:11]
QA, QB
nQA, nQB
out
out
LVDS
DC Input
ä
V
OS
/Δ V
OS
V
DD
20%
80%
80%
20%
t
R
t
F
V
OD
QA, QB
nQA, nQB
Amplitude (dB)
A0
Spectrum of Output Signal Q
MUX
_ISOL
= A0 – A1
(fundamental)
Frequency
ƒ
MUX selects static input
MUX selects active
input clock signal
A1
out
out
LVDS
DC Input
ä
V
OS
/Δ V
OS
V
DD

854S202AYI-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 12:2 Differential LVDS Multiplexer
Lifecycle:
New from this manufacturer.
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