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KSZ8721BLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
Micrel, Inc. KS8721BL/SL
June 2009
10
M9999-062509-1.3
Strapping Options
(1)
Pin Number Pin Name Type
(2)
Pin Function
6, 5,
4, 3
PHYAD[4:1]/
RXD[0:3]
Ipd/O
25
PHYAD0/
INT#
Ipu/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
9
(3)
PCS_LPBK/
RXDV
Ipd/O Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
11
(3)
ISO/RXER Ipd/O Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
21
(3)
RMII/COL Ipd/O Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
22
(3)
RMII_BTB
CRS
Ipd/O
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
PU = Enable.
27
SPD100/
No FEF/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) =
100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
LED2
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU (default) =
Full-duplex. If Duplex is pulled up during reset, this pin is also latched as the Duplex
support in register 4h.
29
NWAYEN/
LED3
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/reset.
PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30 PD# Ipu Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Notes:
1. Strap-in is latched during power-up or reset.
2. Ipu = Input with internal pull-up.
Ipd/O = Input with internal pull-down during reset; output pin otherwise.
Ipu/O = Input with internal pull-up during reset; output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
3. Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in incorrect strapping values latched at reset.
It is recommended that an external pull-down via 1k resistor be used in these applications to augment the 8721’s internal pull-down.
Micrel, Inc. KS8721BL/SL
June 2009
11
M9999-062509-1.3
Functional Description
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3
encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit
nibbles into a 125MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The
serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output
current is set by an external 1% 6.49k resistor for the 1:1 transformer ratio. Its typical rise/fall time of 4ns complies
with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-
T output driver is also incorporated into the 100BASE-TX driver.
100BASE-TX Receive
The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the
equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss
and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize
performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming
signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process
and can self-adjust for environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effects of base line wander and improve dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B
nibbles. A synchronized 25MHz RXC is generated so that the 4B nibbles are clocked out at the negative edge of
RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is
locked to the 25MHz reference clock and both TXC and RXC clocks continue to run.
PLL Clock Synthesizer
The KS8721BL/SL generates 125MHz, 25MHz, and 20MHz clocks for system timing. An internal crystal oscillator circuit
provides the reference clock for the synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic
interference (EMI) and baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding and transmission begins. The KS8721BL/SL continues to
encode and transmit data as long as TXEN remains high. The data transmission ends when TXEN goes low. The last
transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one.
The output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are
internally wave-shaped and pre-emphasized into outputs with typical 2.5V amplitude. The harmonic contents are at
least 27dB below the fundamental when driven by all-ones, Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and
NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent
noise at the RX+ or RX- input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KS8721BL/SL decodes a data frame. This activates the carrier sense (CRS) and
RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in
between data reception.
Micrel, Inc. KS8721BL/SL
June 2009
12
M9999-062509-1.3
SQE and Jabber Function (10BASE-T only)
In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a
test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL
goes high if TXEN is high for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BASE-T
transmitter is re-enabled and COL goes low.
Auto-Negotiation
The KS8721BL/SL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It
automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its
link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in
either full- or half-duplex mode (please refer to “Auto-Negotiation”). Auto-negotiation is disabled in the FX mode.
During auto-negotiation, the contents of Register 4, coded in fast link pulse (FLP), are sent to its link partner under the
conditions of power-on, link-loss, or restart. At the same time, the KS8721BL/SL monitors incoming data to determine
its mode of operation. The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or
100BASE-TX idle is detected. The operation mode is configured based on the following priority:
Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
When the KS8721BL/SL receives a burst of FLP from its link partner with three identical link code words (ignoring
acknowledge bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the
KS8721BL/SL detects the second code words, it then configures itself according to the above-mentioned priority. In
addition, the KS8721BL/SL also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the
KS8721BL/SL automatically configures to match the detected operating speed.
MII Management Interface
The KS8721BL/SL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KS8721BL/SL. The MDIO interface consists of the following:
• A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT).
• A specific protocol that runs across the above-mentioned physical connection that allows one controller to
communicate with multiple KS8721BL/SL devices. Each KS8721BL/SL is assigned an MII address between 0
and 31 by the PHYAD inputs.
• An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions
are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.
The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a
status change on the KS8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits.
Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.
MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access
Controller (MAC) to the KS8721BL/SL, and for receiving data from the line. Normal data transmission is implemented in
4B nibble mode (4-bit wide nibbles).
Transmit Clock (TXC)
The transmit clock is normally generated by the KS8721BL/SL from an external 25MHz reference source at the X1
input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8721BL/SL
normally samples these signals on the rising edge of the TXC.
Receive Clock (RXC)
For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-
negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T links, the
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

KSZ8721BLI

Mfr. #:
Buy KSZ8721BLI
Manufacturer:
Microchip Technology / Micrel
Description:
Ethernet ICs 10/100 BASE-TX/FX Physical Layer Transceiver
Lifecycle:
New from this manufacturer.
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