Micrel, Inc. KS8721BL/SL
June 2009
25
M9999-062509-1.3
10Base-TX Receive
R
IN
RX+/RX– Differential Input
Resistance
8 kW
V
SQ
Squelch Threshold 5MHz square wave 400 mV
10Base-TX Transmit (measured differentially after 1:1 transformer)
Peak Differential Output Voltage 50W from each output to V
DD
2.2 2.8 V V
P
Jitters Added 50W from each output to V
DD
±3.5 ns
t
r
, t
f
Rise/Fall Time 25 ns
Clock Outputs
X1, X2 Crystal Oscillator 25 MHz
RXC
100
Receive Clock, 100TX 25 MHz
Receive Clock, 10T 2.5 MHz RXC
10
Receive Clock Jitters 3.0 ns
(pp)
TXC
100
Transmit Clock, 100TX 25 MHz
Transmit Clock, 10T 2.5 MHz TXC
10
Transmit Clock Jitters 1.8 ns
(pp)
Notes:
1. Exceeding the absolute maximum rating may damage the device. Operating at maximum conditions for extended periods may affect device reliability.
2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level
(Ground to V
DD
)
3. No (HS) heat spreader in this package.
4. Specification for packaged product only.
5. There is 100% data transmission in full-duplex mode and a minimum IPG with a 130-meter cable.
Micrel, Inc. KS8721BL/SL
June 2009
26
M9999-062509-1.3
Timing Diagrams
Figure 4. 10BASE-T MII Transmit Timing
Symbol Parameter Min Typ Max Units
t
SU1
TXD [3:0] Set-Up to TXC High 10 ns
t
SU2
TXEN Set-Up to TXC High 10 ns
t
HD1
TXD [3:0] Hold After TXC High 0 ns
t
HD2
TXEN Hold After TXC High 0 ns
t
CRS1
TXEN High to CRS Asserted Latency 4 BT
(1)
t
CRS2
TXEN Low to CRS De-Asserted Latency 8 BT
t
LAT
TXEN High to TXP/TXM Output (TX Latency) 4 BT
t
SQE
COL (SQE) Delay After TXEN De-Asserted 2.5 µs
t
SQEP
COL (SQE) Pulse Duration 1.0 µs
Table 3. 10BASE-T MII Transmit Timing Parameters
Note:
1. 1BT = 10ns at 10BASE-TX
Micrel, Inc. KS8721BL/SL
June 2009
27
M9999-062509-1.3
Figure 5. 100BASE-T MII Transmit Timing
Symbol Parameter Min Typ Max Units
t
SU1
TXD [3:0] Set-Up to TXC High 10 ns
t
SU2
TXEN Set-Up to TXC High 10 ns
t
HD1
TXD [3:0] Hold After TXC High 0 ns
t
HD2
TXER Hold After TXC High 0 ns
t
HD3
TXEN Hold After TXC High 0 ns
t
CRS1
TXEN High to CRS Asserted Latency 4 BT
(1)
t
CRS2
TXEN Low to CRS De-Asserted Latency 4 BT
t
LAT
TXEN High to TXP/TXM Output (TX Latency) 9 BT
Table 4. 100BASE-T MII Transmit Timing Parameters
Note:
1. 1BT = 10ns at 100BASE-TX

KSZ8721BLI

Mfr. #:
Manufacturer:
Microchip Technology / Micrel
Description:
Ethernet ICs 10/100 BASE-TX/FX Physical Layer Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
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