IRF9620PBF Datasheet IRF9620, IRF9620L, IRF9620PBF | P4-P6

www.vishay.com Document Number: 91082

4 S11-0512-Rev. B, 21-Mar-11

This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF9620, SiHF9620

Vishay Siliconix

Fig. 6 - Typical Transconductance vs. Drain Current

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Breakdown Voltage vs. Temperature

Fig. 9 - Normalized On-Resistance vs. Temperature

Fig. 10 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 11 - Typical Gate Charge vs. Gate-to-Source Voltage

4.0

g

fs

,Transconductance (S)

I

D

,

Drain Current (A)

- 1 - 2 - 3 - 4 - 5

0

T

J

= 25

°

C

T

J

= - 55

°

C

91082_06

T

J

= 125

°

C

80 µs Pulse Test

V

DS

> I

D(on)

x R

DS(on)

max.

3.2

2.4

1.6

0.8

0.0

T

J

= 25 °C

T

J

= 150 °C

- 20

V

SD

, Source-to-Drain Voltage (V)

I

DR

, Reverse Drain Current (A)

- 2.0

- 6.8

- 5.6- 4.4- 3.2

91082_07

- 0.1

- 0.2

- 1.0

- 2

- 5

- 10

- 8.0

- 0.5

91082_08

T

J

, Junction Temperature (°C)

BV

DSS

, Drain-to-Source Breakdown

1.25

Voltage (Normalized)

1.15

0.75

0.85

0.95

1.05

- 40

160

120

80400

91082_09

T

J

, Junction Temperature (°C)

R

DS(on)

, Drain-to-Source On Resistance

2.5

(Normalized)

2.0

0.0

0.5

1.0

1.5

- 40

160

12080400

I

D

= - 1.0 A

V

GS

= - 10 V

91082_10

V

DS

, Drain-to-Source Voltage (V)

C, Capacitance (pF)

500

0

100

200

300

400

0 - 50- 40- 30- 20

- 10

C

iss

C

rss

C

oss

V

GS

= 0 V, f = 1 MHz

C

iss

= C

gs

+ C

gd

, C

ds

Shorted

C

rss

= C

gd

C

oss

= C

ds

+

C

gs

, C

gd

C

gs

+ C

gd

≈ C

gs

+ C

gd

Q

G

, Total Gate Charge (nC)

Negative V

GS

, Gate-to-Source Voltage (V)

20

16

12

8

0

4

04 16128

V

DS

= - 40 V

V

DS

= - 60 V

For test circuit

see figure 18

V

DS

= - 100 V

91082_11

I

D

= - 3.5 A

20

Document Number: 91082 www.vishay.com

S11-0512-Rev. B, 21-Mar-11 5

This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF9620, SiHF9620

Vishay Siliconix

Fig. 12 - Typical On-Resistance vs. Drain Current

Fig. 13 - Maximum Drain Current vs. Case Temperature

Fig. 14 - Power vs. Temperature Derating Curve

Fig. 15 - Clamped Inductive Test Circuit

Fig. 16 - Clamped Inductive Waveforms

Fig. 17a - Switching Time Test Circuit

Fig. 17b - Switching Time Waveforms

91082_12

I

D

, Drain Current (A)

R

DS(on)

, Drain-to-Source

R

DS(on)

measured with current

pulse of 2.0 µs duration. Initial

T

J

= 25 °C. (Heating effect of

2.0 µs pulse is minimal.)

0

1

2

3

4

5

0 - 20- 16- 8- 4 - 12

On Resistance (Ω)

V

GS

= - 10 V

V

GS

= - 20 V

150

Negative I

D

, Drain Current (A)

T

C

, Case Temperature (°C)

0.0

1.5

2.0

2.5

3.0

3.5

25

91082_13

1251007550

1.0

0.5

T

C

, Case Temperature (°C)

P

D

, Power Dissipation (W)

40

35

20

0

5

0 20 100806040

91082_14

140

120

30

25

15

10

0.05 Ω

D.U.T.

L

V

DS

+

-

V

DD

V

GS

= - 10 V

Var y t

p

to obtain

required I

L

t

p

V

DD

= 0.5 V

DS

E

C

= 0.75 V

DS

E

C

I

L

V

DD

V

DS

t

p

E

C

I

L

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

- 10 V

+

-

V

DS

V

DD

V

GS

10 %

90 %

V

DS

t

d(on)

t

r

t

d(off)

t

f

www.vishay.com Document Number: 91082

6 S11-0512-Rev. B, 21-Mar-11

This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF9620, SiHF9620

Vishay Siliconix

Fig. 18a - Basic Gate Charge Waveform Fig. 18b - Gate Charge Test Circuit

Fig. 19 - For P-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91082

.

Q

GS

Q

GD

Q

G

V

G

Charge

- 15 V

D.U.T.

- 3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

P.W.

Period

dI/dt

Diode recovery

dV/dt

Body diode forward drop

Body diode forward

current

Driver gate drive

Inductor current

D =

P.W.

Period

+

-

+

Peak Diode Recovery dV/dt Test Circuit

• dV/dt controlled by R

g

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

• Compliment N-Channel of D.U.T. for driver

V

DD

• I

SD

controlled by duty factor “D”

Note

a. V

GS

= - 5 V for logic level and - 3 V drive devices

V

GS

= - 10 V

a

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

V

DD

Re-applied

voltage

Ripple ≤ 5 %

I

SD

Reverse

recovery

current

IRF9620PBF

IRF9620PBF

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