3
AT29BV020
0402D–FLASH–05/02
Any attempt to write to the device without the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however, for the duration of t
WC
, a read oper-
ation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed
by applying a low pulse on the WE
or CE input with CE or WE low (respectively) and OE high.
The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is
latched by the first rising edge of CE
or WE.
The 256 bytes of data must be loaded into each sector. Any byte that is not loaded during the
programming of its sector will be indeterminated. Once the bytes of a sector are loaded into
the device, they are simultaneously programmed during the internal programming period.
After the first data byte has been loaded into the device, successive bytes are entered in the
same manner. Each new byte to be programmed must have its high-to-low transition on WE
(or CE) within 150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a
high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load
period will end and the internal programming period will start. A8 to A17 specify the sector
address. The sector address must be valid during each high-to-low transition of WE
(or CE).
A0 to A7 specify the byte address within the sector. The bytes may be loaded in any order;
sequential loading is not required.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT29BV020 in the following ways: (a) V
CC
sense – if V
CC
is below 2.0V (typical),
the program function is inhibited; (b) V
CC
power on delay – once V
CC
has reached the V
CC
sense level, the device will automatically time out 10 ms (typical) before programming; (c) Pro-
gram inhibit – holding any one of OE
low, CE high or WE high inhibits program cycles; and (d)
Noise filter – pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a pro-
gram cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and
control inputs (OE
,CEand WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to V
CC
+0.6V.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product. In addition, users may wish to use the software product identi-
fication mode to identify the part (i.e., using the device code), and have the system software
use the appropriate sector size for program operations. In this manner, the user can have a
common board design for 256K to 4-megabit densities and, with each density’ssectorsizein
a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both methods of identification.
DATA
POLLING: The AT29BV020 features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte loaded will result in the com-
plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during
the program cycle.
TOGGLE BIT: In addition to DATA
polling the AT29BV020 provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
