TFA9891 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product short data sheet Rev. 1 — 21 December 2016 12 of 24
NXP Semiconductors
TFA9891
9.5 V boosted audio system with adaptive sound maximizer and
speaker protection
10. I
2
C-bus interface and register settings
The TFA9891 supports the 400 kHz I
2
C-bus microcontroller interface mode standard. The
I
2
C-bus is used to control the TFA9891 and to transmit and receive data. The TFA9891
can only operate in I
2
C slave mode, as a slave receiver or as a slave transmitter.
10.1 TFA9891 addressing
The TFA9891 is accessed via an 8-bit code; see Table 5. Bits 1 to 7 contain the device
address. Bit 0 (R/W
) indicates whether a read (1) or a write (0) operation has been
requested. Four separate addresses are supported for stereo applications. Address
selection is via pins ADS1 and ADS2. The levels on pins ADS1 and ADS2 determine the
values of bits 1 and 2, respectively, of the device address, as detailed in Table 5
. The
generic address is independent of pins ADS1 and ADS2.
10.2 I
2
C-bus write cycle
The sequence of events that is followed when writing data to the I
2
C-bus registers of
TFA9891 is specified in Table 6
. 1 byte is transmitted at a time. Each register stores 2
bytes of data. Data is always written in byte pairs. Data transfer is always MSB first.
The write cycle sequence using SDA is as follows:
• The microcontroller asserts a start condition (S).
• The microcontroller transmits the 7-bit device address of the TFA9891, followed by
the R/W
bit set to 0.
• The TFA9891 asserts an acknowledge (A).
• The microcontroller transmits the 8-bit TFA9891 register address to which the first
data byte is written.
• The TFA9891 asserts an acknowledge.
• The microcontroller transmits the first byte (the most significant byte).
• The TFA9891 asserts an acknowledge.
• The microcontroller transmits the second byte (the least significant byte).
• The TFA9891 asserts an acknowledge.
Table 5. Address selection via pins ADS1 and ADS2
ADS2 pin voltage (V) ADS1 pin voltage (V) Address Function
0 0 01101000 for write mode
01101001 for read mode
0V
DDD
01101010 for write mode
01101011 for read mode
V
DDD
0 01101100 for write mode
01101101 for read mode
V
DDD
V
DDD
01101110 for write mode
01101111 for read mode
don’t care don’t care 00011100 (generic address) for write mode
don’t care don’t care 00011101 (generic address) for read mode
