TFA9891 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product short data sheet Rev. 1 — 21 December 2016 13 of 24
NXP Semiconductors
TFA9891
9.5 V boosted audio system with adaptive sound maximizer and
speaker protection
• The microcontroller can either assert the stop condition (P) or continue transmitting
data by sending another pair of data bytes, repeating the sequence from step 6. In the
latter case, the targeted register address has been auto-incremented by the TFA9891.
[1] ACK stands for acknowledge.
10.3 I
2
C-bus read cycle
The sequence of events that is followed when reading data from the I
2
C-bus registers of
TFA9891 is specified in Table 7
. 1 byte is transmitted at a time. Each of the registers
stores 2 bytes of data. Data is always written in byte pairs. Data transfer is always MSB
first.
The read cycle sequence using SDA is as follows:
• The microcontroller asserts a start condition (S)
• The microcontroller transmits the 7-bit device address of the TFA9891, followed by
the R/W
bit set to 0
• The TFA9891 asserts an acknowledge (A)
• The microcontroller transmits the 8 bit TFA9891 register address from which the first
data byte is read
• The TFA9891 asserts an acknowledge
• The microcontroller asserts a repeated start (Sr)
• The microcontroller retransmits the device address followed by the R/W bit set to 1
• The TFA9891 asserts an acknowledge
• The TFA9891 transmits the first byte (the MSB)
• The microcontroller asserts an acknowledge
• The TFA9891 transmits the second byte (the LSB)
• The microcontroller asserts either an acknowledge or a negative acknowledge (NA)
– If the microcontroller asserts an acknowledge, TFA9891auto increments the target
register address and steps 9 to 12 are repeated
– If the microcontroller asserts a negative acknowledge, the TFA9891 frees the
I
2
C-bus and the microcontroller generates a stop condition (P)
Table 6. I
2
C-bus write cycle
Start TFA9891
address
R/W ACK
[1]
TFA9891 first
register address
ACK
[1]
MSB ACK
[1]
LSB ACK
[1]
More
data...
Stop
S01101A
2
A
1
0 A ADDR A MS1 A LS1 A <....> P
Table 7. I
2
C-bus read cycle
Start TFA9891
address
R/W ACK First
register
addres
s
ACK R
es
ta
rt
TFA9891
address
R/
W
ACK MSB ACK LSB ACK More
data...
ACK Stop
S01101A
2
A
1
0 A ADDR A Sr 11011A
2
A
1
1 A MS1 A LS1 A <....> NA P
