LTC2461/LTC2463
8
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APPLICATIONS INFORMATION
current by approximately 50%. While in the Nap state,
the reference remains powered up. To power down the
reference in addition to the converter, the user can select
the SLEEP mode during the DATA INPUT/OUTPUT state.
Once the next conversion is complete, SLEEP state is
entered and power is reduced to 200nA. The reference
is powered up once a valid read/write is acknowledged.
The reference startup time is 12ms (if the reference and
compensation capacitor values are both 0.1μF).
Power-Up Sequence
When the power supply voltage (V
CC
) applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When V
CC
rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2461/LTC2463
start a conversion cycle and follow the succession of states
shown in Figure 2. The reference startup time following a
POR is 12ms (C
COMP
= C
REFOUT
= 0.1μF). The first conver-
sion following power-up will be invalid since the reference
voltage has not completely settled. The first conversion
following power up can be discarded using the data abort
command or simply read and ignored. The following con-
versions are accurate to the device specifications.
Ease of Use
The LTC2461/LTC2463 data output has no latency, filter
settling delay or redundant results associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog input voltages requires no
special actions.
The LTC2461/LTC2463 perform offset calibrations every
conversion cycle. This calibration is transparent to the
user and has no effect upon the cyclic operation described
previously. The advantage of continuous calibration is
stability of the ADC performance with respect to time and
temperature.
The LTC2461/LTC2463 include a proprietary input sampling
scheme that reduces the average input current by several
orders of magnitude when compared to traditional delta-
sigma architectures. This allows external filter networks
to interface directly to the LTC2461/LTC2463. Since the
average input sampling current is 50nA, an external RC
lowpass filter using 1kΩ and 0.1µF results in <1LSB
additional error. Additionally, there is negligible leakage
current between IN
+
and IN
–
.
Input Voltage Range (LTC2461)
Ignoring offset and full-scale errors, the LTC2461 will
theoretically output an “all zero” digital result when the
input is at ground (a zero scale input) and an “all one”
digital result when the input is at V
REF
(V
REFOUT
= 1.25V).
In an underrange condition, for all input voltages below
zero scale, the converter will generate the output code 0. In
an overrange condition, for all input voltages greater than
V
REF
, the converter will generate the output code 65535.
For applications that require an input range greater than
0V to 1.25V, please refer to the LTC2451.
Input Voltage Range (LTC2463)
As mentioned in the Output Data Format section, the output
code is given as 32768 • (V
IN
+
– V
IN
–
)/V
REF
+ 32768. For
(V
IN
+
– V
IN
–
) ≥ V
REF
, the output code is clamped at 65535
(all ones). For (V
IN
+
– V
IN
–
) ≤ –V
REF
, the output code is
clamped at 0 (all zeroes).
The LTC2463 includes a proprietary architecture that
can, typically, digitize each input up to 8 LSBs above
