LNBP8L - LNBP9L - LNBP10L - LNBP11L Electrical characteristics
7/21
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
ILT
3-state control pin input
current LOW
V
ILT
= 0 V, EN/VSEL +180 µA
V
IL
Control input logic LOW TEN, LLC 0.8 V
V
IH
Control input logic HIGH TEN, LLC 2.5 V
I
IH
Control pins input current V
IH
= 5 V, TEN, LLC 20 µA
I
CC
Supply current
Output disabled EN/VSEL=High
impedance (floating)
1.7 2.4 mA
Output enabled EN/VSEL=HIGH,
TEN=HIGH, I
OUT
= 500 mA
3.7 6.3 mA
T
OFF
Dynamic overload
protection OFF time
Output shorted, C
EXT
= 4.7 µF
(2)
1000 ms
T
ON
Dynamic overload
protection ON time
Output shorted, C
EXT
= 4.7 µF
(2)
T
OFF
/12
ms
I
OBK
Output backward current Output forced to 21 V 6 mA
T
SHDN
Thermal shutdown
threshold
165 °C
ΔT
SHDN
Thermal shutdown
hysteresis
25 °C
1. For IPPAK package V
CC1
and V
CC2
are internally connected to the pin 1 (V
CC
) to be supplied in the range from 22 V up to
25 V
2. Only DFN package
3. Guaranteed by design
Table 5. Electrical characteristics (continued)
Refer to the typical application circuits in Figure 3 and Figure 4, V
CC1
= 16 V, V
CC2
= 23 V
(1)
, EN/VSEL =
LOW, TEN = LLC = LOW, EXTM = FLOATING, I
OUT
= 50 mA, T
J
= 0 °C to 85 °C, unless otherwise stated.
Typical values are referred to T
J
= 25 °C
Typical application circuits LNBP8L - LNBP9L - LNBP10L - LNBP11L
8/21
5 Typical application circuits
Note: In a single supply configuration with the DFN package, an R
1
resistor in the 12-15
Ω
range
is recommended to reduce device power dissipation during the 13 V output condition. The
resistor can be omitted, but the power dissipation will increase.
Figure 3. Single input supply voltage solution for IPPAK package versions
VCC
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
23V
LNBP8/9L
C2
220nF
C1
10µF
LNB OUTPUT
C3
100nF
D2
1N5818
VCC
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
23V
LNBP8/9L
C2
220nF
C1
10µF
LNB OUTPUT
C3
100nF
D2
1N5818
VCC
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
23V
LNBP8/9L
C2
220nF
C1
10µF
LNB OUTPUT
C3
100nF
D2
1N5818
VCC
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
23V
LNBP8/9L
C2
220nF
C1
10µF
LNB OUTPUT
C3
100nF
D2
1N5818
Figure 4. Dual input supply voltage solution for DFN8 (5 x 6 mm) package versions
VCC1
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1 1N4001
MCU I/Os
16V
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
D3 1N4001
23V
C5
220nF
C4
10µF
CEXT
C6
4.7µF
VCC1
EN/VSEL (Tristate
OUTPUT
GND
EXTM or TEN
D1 1N4001
MCU I/Os
16V
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
D3 1N4001
23V
C5
220nF
C4
10µF
CEXT
C6
4.7µF
VCC1
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1 1N4001
MCU I/Os
16V
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
D3 1N4001
23V
C5
220nF
C4
10µF
CEXT
C6
4.7µF
VCC1
EN/VSEL (Tristate
OUTPUT
GND
EXTM or TEN
D1 1N4001
MCU I/Os
16V
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
D3 1N4001
23V
C5
220nF
C4
10µF
CEXT
C6
4.7µF
Figure 5. Single input supply voltage solution for DFN8 (5 x 6 mm) package versions
VCC1
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
23V
C4
220nF
CEXT
C5
4.7µF
R1
15 Ohm >3W
VCC1
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
23V
C4
220nF
CEXT
C5
4.7µF
R1
15 Ohm >3W
VCC1
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
23V
C4
220nF
CEXT
C5
4.7µF
R1
15 Ohm >3W
VCC1
EN/VSEL (Tristate )
OUTPUT
GND
EXTM or TEN
D1
1N4001
MCU I/Os
LNBP10/11L
C2
220nF
C1
10µF
C3
100nF
D2
1N5818
LNB OUTPUT
LLC
VCC2
23V
C4
220nF
CEXT
C5
4.7µF
R1
15 Ohm >3W
LNBP8L - LNBP9L - LNBP10L - LNBP11L Detailed description and application hints
9/21
6 Detailed description and application hints
The LNBPxx is made up of several functional blocks (see Figure 1 on page 3), as described
below:
1. The oscillator is activated by setting the ENT pin (enable tone) = H, and is factory-
trimmed at 22 kHz ± 2 kHz, eliminating the need to use external trimming. The rising
and falling edges are maintained in the 5 to 15 µs range (10 µs typ.), to avoid RF
pollution of the receiver. The duty cycle is 50% typ. It modulates the DC output with a ±
0.325 V typ. amplitude and 0 V average. The presence of this signal usually gives the
LNB information about the band to be received.
2. The 3-state enable & V
OUT
selection block, selects the two output voltages or sets the
IC to shutdown mode, depending on the voltage applied on the EN/VSEL pin.
When EN/VSEL is set high (EN/VSEL > 2.2 V), an 18 V output voltage is selected;
when the EN/VSEL is set low (EN/VSEL < 0.8 V), a 13 V output voltage is selected.
If the EN/VSEL pin is left floating (high impedance) or if the pin is set in a range from
1.2 V to 1.8 V (1.5 V typ.), the IC goes into shutdown mode and the output voltage will
be set to 0 V.
This feature changes the LNB polarization type. The LNB switches to horizontal or
vertical polarization depending on the supply voltage it gets from the receiver.
3. For the DFN package, in order to keep the power dissipation of the device as low as
possible, the input selector automatically selects V
CC1
; that is, the lowest input voltage,
when 13 V output is selected (i.e. EN/VSEL is low). If the 18 V output is selected (i.e.
EN/VSEL is high), the V
CC2
input pin is selected. For example, power dissipation at
I
OUT
= 350 mA is:
P
D
= (23 - 18) x 0.35 = 1.75 W
with V
CC2
= 23 V (voltage on the V
CC2
pin) and V
OUT
= 18 V, and
P
D
= (16 - 13) x 0.35 = 1.05 W
with V
CC1
= 16 V (voltage on the V
CC1
pin) and V
OUT
= 13 V
For IPPAK package, V
CC1
and V
CC2
are internally connected and must be supplied from a
single input voltage line (22 V min.) to the V
CC
pin. In this case the worst case power
dissipation is 13 V output. For example: at I
OUT
= 350 mA and V
CC
= 23 V (voltage on the
V
CC
pin):
P
D
= (23 - 13) x 0.35 = 3.5 W
4. The line length compensation function is useful when the antenna is connected to the
receiver by a long coaxial cable that adds a considerable DC voltage drop. When the
LCC pin is H, the output voltage selected is increased by about 1 V. This function is
available for the DFN package only.
5. The reference drives all the internal blocks that require a high-precision thermally
compensated voltage source.
6. The LNBPxx has two different protection features, and both turn off the outputs. The
first one protects against overheating (i.e. for T
J
150 °C), and the second against
overload conditions (i.e. for output current > 550 mA) or short-circuit:
a) In the thermal protection case the output is disabled until the chip temperature has
fallen below 140 °C typ. and the LNBPxx output is restored.
b) The overload protection case occurs when output current request is 500 mA. For
the DFN package only, the IC features dynamic overload and short-circuit

LNBP10LPUR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC REG CONV RECVRS 1OUT 8DFN
Lifecycle:
New from this manufacturer.
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