NCP1380
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4
INTERNAL CIRCUIT ARCHITECTURE
FB
Ct
ICt
+
+
ZCD
Laux
10 V
ESD
Vth
DRV
dema g
S
R
Q
CS
Rsense
LEB 1
+
/ 4
VDD
VDD
Soft-start
VCC
aux
V
CC
management
latch
VDD
Rpullup
faul t
DRV
gate
gra nd
reset
gra nd
reset
gra nd
reset
DRV
clamp
Soft−sta rt end ? the n 1
else 0
A:
l a tc he d
IpFlag
+
SS end
IpFlag
PWMreset
P W Mr eset
GND
Up
Down
TIM ER
Reset
VCCstop
BO reset
LOGI C BLOCK
VDD
Faul t
VCC
V
OVP
I
OTP(REF)
OPP
V
ILIMIT
+
VDD
+
V
OTP
SS end
nois e del ay
nois e del ay
5 ms
Time Out
LEB 2
+
V
CS(stop)
CsS top
CsS top
LEB 2 is shorter than LEB 1
40 ms
Time Out
SS end
The 40 ms Time Out is active
only during soft−s tar t
SS end
Figure 3. Internal Circuit Architecture for Versions A and B
S
R
Q
Q
Q
I
peak(VCO)
= 17.5% V
ILIMIT
Ct setpoi nt
Ct
Discharge
3 ms blanking
NCP1380
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5
FB
Ct
ICt
+
+
ZCD
Laux
10 V
ESD
Vth
DRV
dema g
S
R
Q
/ 4
VCC
VDD
VDD
VCC
aux
V
CC
management
latch
VDD
Rpullup
faul t
DRV
gate
gra nd
reset
gra nd
reset
gra nd
reset
DRV
clamp
IpFlag
P W Mreset
OVP/BO
GND
Up
Down
TIMER
Res et
VCCstop
H
V
+
IBO
nois e del ay
VBO
BO res et
+
Vclamp
VOVP
noise de lay
BO reset
LOGIC BLOCK
VDD
Rclamp
VDD
C :
l a tc he d
CS
Rsense
LEB 1
+
Soft-start
Soft−sta rt e nd ? then 1
else 0
IpFlag
+
SS end
P W Mreset
OPP
V
ILIMIT
LEB 2
+
V
CS( st op)
CsS top
LEB 2 is shorter than LEB 1
CsS top
5 ms
Time Out
40 ms
Time Out
SS end
The 40 ms Time Out is active
only during soft−s tar t
SS end
Figure 4. Internal Circuit Architecture for Versions C and D
S
R
Q
Q
Q
I
peak(VCO)
= 17.5% V
ILIMIT
Ct setpoint
3 ms blanking
Ct
discharge
NCP1380
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6
MAXIMUM RATINGS
Symbol Rating Value Unit
V
CC(MAX)
I
CC(MAX)
Maximum Power Supply voltage, V
CC
pin, continuous voltage
Maximum current for V
CC
pin
−0.3 to 28
±30
V
mA
V
DRV(MAX)
I
DRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3 to 20
±1000
V
mA
V
MAX
I
MAX
Maximum voltage on low power pins (except pins DRV and V
CC
)
Current range for low power pins (except pins ZCD, DRV and V
CC
)
−0.3 to 10
±10
V
mA
I
ZCD(MAX)
Maximum current for ZCD pin +3 / −2 mA
R
q
JA
Thermal Resistance Junction−to−Air 120 °C/W
T
J(MAX)
Maximum Junction Temperature 150 °C
Operating Temperature Range −40 to +125 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, HBM Model (Note 1) 4 kV
ESD Capability, MM Model (Note 1) 200 V
ESD Capability, CDM Model (Note 1) 2 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 4000 V per JEDEC Standard JESD22, Method A114E
Machine Model 200 V per JEDEC Standard JESD22, Method A115A
Charged Device Model 2000 V per JEDEC Standard JESD22−C101D.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T
J
= 25°C, V
CC
= 12 V, V
ZCD
= 0 V,
V
FB
= 3 V, V
CS
= 0 V, V
fault
= 1.5 V, C
T
= 680 pF) For min/max values T
J
= −40°C to +125°C, Max T
J
= 150°C, V
CC
= 12 V)
Symbol
Condition Min Typ Max Unit
SUPPLY SECTION − STARTUP AND SUPPLY CIRCUITS
V
CC(on)
V
CC(off)
V
CC(HYS)
V
CC(latch)
V
CC(reset)
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis V
CC(on)
− V
CC(off)
Clamped V
CC
when latched−off
Internal logic reset
V
CC
increasing
V
CC
decreasing
V
CC
decreasing, I
CC
= 30 mA
16
8.3
7.2
6.2
6
17
9
8.0
7.2
7
18
9.4
9.2
8.2
8
V
t
VCC(off)
t
VCC(reset)
V
CC(off)
noise filter
V
CC(reset)
noise filter
5
20
ms
I
CC(start)
Startup current FB pin open
V
CC
= V
CC(on)
− 0.5 V
10 20
mA
I
CC(disch)
Current that discharges V
CC
when the controller
gets latched
V
CC
= 12 V 3.0 4.0 5.0 mA
I
CC(latch)
Current into V
CC
that keeps the controller latched
(Note 3)
V
CC
= V
CC(latch)
30
mA
I
CC1
I
CC2
I
CC3A
I
CC3B
Supply Current
Device Disabled/Fault (Note 3) B, C, and D only
Device Enabled/No output load on pin 5
Device Switching (F
SW
= 65 kHz)
Device Switching VCO mode
V
CC
> V
CC(off)
F
sw
= 10 kHz
C
DRV
= 1 nF, F
SW
= 65 kHz
C
DRV
= 1 nF, V
FB
= 1.25 V
1.7
1.7
2.65
2.0
2.0
2.0
3.0
mA
CURRENT COMPARATOR − CURRENT SENSE
V
ILIM
Current Sense Voltage Threshold V
FB
= 4 V, V
CS
increasing 0.76 0.8 0.84 V
t
LEB
Leading Edge Blanking Duration for V
ILIM
Minimum on time minus t
ILIM
210 275 330 ns
I
bias
Input Bias Current (Note 3) DRV high −2 2
mA
t
ILIM
Propagation Delay V
CS
> V
ILIM
to DRV turn−off 125 175 ns
I
peak(VCO)
Percentage of maximum peak current level at
which VCO takes over (Note 4)
V
FB
= 0.4 V, V
CS
increasing 15.4 17.5 19.6 %

NCP1380DDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers QUASI-RES CUR MODE CONTRL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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