50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
DEPTH EXPANSION CONFIGURATION IN SINGLE DATA RATE
(FWFT MODE ONLY)
The IDT72T2098 can easily be adapted to applications requiring depths
greater than 32,768 when the x20 Input or x20 Output bus width is selected,
65,536 for the IDT72T20108, 131,072 for the IDT72T20118 and 262,144 for
the IDT72T20128. When both x10 Input and x10 Output bus widths are
selected, depths greater than 65,536 can be adapted for the IDT72T2098,
131,072 for the IDT72T20108, 262,144 for the IDT72T20118 and 524,288 for
the IDT72T20128. In FWFT mode, the FIFOs can be connected in series (the
data outputs of one FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO. Figure 32 shows a
depth expansion using two IDT72T2098/72T20108/72T20118/72T20128
devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. Also, the devices must be operating in
Single Data Rate mode since that is the only mode available in FWFT. The first
word written to an empty configuration will pass from one FIFO to the next ("ripple
down") until it finally appears at the outputs of the last FIFO in the chain – no read
operation is necessary but the RCLK of each FIFO must be free-running. Each
time the data word appears at the outputs of one FIFO, that device's OR line goes
LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK period.
Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
Figure 32. Block Diagram of Depth Expansion in Single Data Rate Mode
For the x20 Input or x20 Output bus Width: 65,536 x 20, 131,072 x 20, 262,144 x 20 and 524,288 x 20
For both x10 Input and x10 Output bus Widths: 131,072 x 10, 262,144 x 10, 524,288 x 10 and 1,048,576 x 10
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5996 drw35
n
n n
FWFT FWFT
FWFT
IDT
72T2098
72T20108
72T20118
72T20128
RCS
READ CHIP SELECT
RCS
IDT
72T2098
72T20108
72T20118
72T20128
