AD7821
REV. B
–3–
TIMING CHARACTERISTICS
1
(V
DD
= +5 V 5%, V
SS
= 0 V or –5 V 5%; Unipolar or Bipolar Input Range)
Limit at Limit at
Limit at +25CT
MIN
, T
MAX
T
MIN
, T
MAX
Parameter (All Versions) (K, B Versions) (T Version) Unit Conditions/Comments
t
CSS
000ns min CS to RD/WR Setup Time
t
CSH
000ns min CS to RD/WR Hold Time
t
RDY
2
70 85 100 ns max CS to RDY Delay. Pull-Up
Resistor 5 k
t
CRD
700 875 975 ns max Conversion Time (RD Mode)
t
ACC0
3
Data Access Time (RD Mode)
t
CRD
+ 25 t
CRD
+ 30 t
CRD
+ 35 ns max C
L
= 20 pF
t
CRD
+ 50 t
CRD
+ 65 t
CRD
+ 75 ns max C
L
= 100 pF
t
INTH
2
50 ns typ RD to INT Delay (RD Mode)
80 85 90 ns max
t
DH
4
15 15 15 ns min Data Hold Time
60 70 80 ns max
t
P
350 425 500 ns min Delay Time Between Conversions
t
WR
250 325 400 ns min Write Pulsewidth
10 10 10 µs max
t
RD
250 350 450 ns min Delay Time between WR and RD Pulses
t
READ1
160 205 240 ns min RD Pulsewidth (WR-RD Mode, see Figure 12b)
Determined by t
ACC1
t
ACC1
3
Data Access Time (WR-RD Mode, see Figure 12b)
160 205 240 ns max C
L
= 20 pF
185 235 275 ns max C
L
= 100 pF
t
RI
150 185 220 ns max RD to INT Delay
t
INTL
2
380 ns typ WR to INT Delay
500 610 700 ns max
t
READ2
65 75 85 ns min RD Pulsewidth (WR-RD Mode, see Figure 12a)
Determined by t
ACC2
Data Access Time (WR-RD Mode, see Figure 12a)
t
ACC2
3
65 75 85 ns max C
L
= 20 pF
90 110 130 ns max C
L
= 100 pF
t
IHWR
2
80 100 120 ns max WR to INT Delay (Stand-Alone Operation)
t
ID
3
Data Access Time after INT
(Stand-Alone Operation)
30 35 40 ns max C
L
= 20 pF
45 60 70 ns max C
L
= 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
a. High Z to V
OH
b. High Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
a. V
OH
to High Z b. V
OL
to High Z
Figure 2. Load Circuits for Data Hold Time Test
ORDERING GUIDE
Total
Temperature Unadjusted Package
Model
1
Range Error (LSB) Option
2
AD7821KN –40°C to +85°C ±1 max N-20
AD7821KP –40°C to +85°C ±1 max P-20A
AD7821KR –40°C to +85°C ±1 max RW-20
AD7821BQ –40°C to +85°C ±1 max Q-20
AD7821TQ –55°C to +125°C ±1 max Q-20
AD7821TE –55°C to +125°C ±1 max E-20A
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
AD7821
REV. B
–4–
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, + 7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, + 7 V
Digital Input Voltage to GND
(Pins 6–8, 13) . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(Pins 2–5, 9, 14–18) . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
(+) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
REF
(–) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
IN
to GND . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
DIP AND SOIC LCCC PLCC
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7821 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1V
IN
Analog Input: Range V
REF
(–) V
IN
V
REF
(+)
2 DB0 Three-State Data Output (LSB)
3–5 DB1–DB3 Three-State Data Outputs
6 WR/RDY WRITE control input/READY status output. See Digital Interface section.
7 MODE Mode Selection Input. It determines whether the device operates in the WR-RD or RD mode. This input is internally
pulled low through a 50 µA current source. See Digital Interface section.
8 RD READ Input. RD must be low to access data from the part. See Digital Interface section.
9 INT INTERRUPT Output. INT going low indicates that the conversion is complete. INT returns high on the rising
edge of CS or RD. See Digital Interface section.
10 GND Ground
11 V
REF
(–) Lower limit of reference span.
Range: V
SS
V
REF
(–) V
REF
(+).
12 V
REF
(+) Upper limit of reference span.
Range: V
REF
(–) < V
REF
(+) V
DD
.
13 CS Chip Select Input. The device is selected when this input is low.
14–16 DB4–DB6 Three-State Data Outputs
17 DB7 Three-State Data Output (MSB)
18 OFL Overflow Output. If the analog input is higher than (V
REF
(+) – 1/2 LSB), OFL will be low at the end of conversion. It
is a non-three-state output which can be used to cascade two or more devices to increase resolution.
19 V
SS
Negative Supply Voltage
V
SS
= 0 V; Unipolar Operation
V
SS
= –5 V; Bipolar Operation
20 V
DD
Positive Supply Voltage, +5 V
AD7821
REV. B
–5–
TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)
An ADC with 8-bit resolution can resolve one part in 2
8
(1/256
of full scale). For the AD7821 operating in either the unipolar
or bipolar input range with 5 V full scale, one LSB is 19.53 mV.
TOTAL UNADJUSTED ERROR
This is a comprehensive specification which includes relative
accuracy, offset error, and full-scale error.
SLEW RATE
Slew rate is the maximum allowable rate of change of input
signal such that the digital sample values are not in error.
TOTAL HARMONIC DISTORTION (THD)
Total harmonic distortion is the ratio of the square root of the
sum of the squares of the rms value of the harmonics to the rms
value of the fundamental. For the AD7821, total harmonic dis-
tortion is defined as
20
2
2
3
2
4
2
5
2
6
2
1
log
VVVVV
V
dB
++++
()
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
, V
4
,
V
5
, and V
6
are the rms amplitudes of the individual harmonics.
INTERMODULATION DISTORTION
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m+n), at sum and difference frequencies of
mfa+nfb, where m, n = 0, 1, 2, 3…. Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), and the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb). For the AD7821 intermodulation distortion is calcu-
lated separately for both the second and third order terms.
SIGNAL-TO-NOISE RATIO (SNR)
Signal-to-noise ratio is measured signal-to-noise at the output of
the ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all nonfundamental signals (excluding
dc) up to half the sampling frequency. SNR is dependent on the
number of quantization levels used in the digitization process.
The theoretical SNR for a sine wave input is given by:
SNR N dB=+
()
602 176..
where N is the number of bits in the ADC. Thus, for an ideal
8-bit ADC, SNR = 50 dB.
PEAK HARMONIC OR SPURIOUS NOISE
Peak harmonic or spurious noise is the rms value of the largest
nonfundamental frequency (excluding dc) up to half the sam-
pling frequency to the rms value of the fundamental.

AD7821KPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Hi Spd uP-Compatible CMOS 8B Sampling
Lifecycle:
New from this manufacturer.
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