LTC3725EMSE#TRPBF Datasheet LTC3725EMSE#TRPBF, LTC3725IMSE#TRPBF, LTC3725IMSE#PBF | P10-P12

LTC3725

3725fa

exceeds 1.26V the gate drive is immediately turned “off.”

Note that this is not considered a fault condition and the

LTC3725 can run indefinitely with the switch duty cycle

being determined by the volt-second limit circuit. The duty

cycle is always limited to 75% to ensure that the power

transformer flux always has time to reset before the start

of the next cycle.

In an alternate application, the volt-second limit can be

used for open-loop regulation of the output against changes

in V

Current Limit

Current limit for the LTC3725 is principally a safety feature

to protect the converter and is not part of a control

function. The current that flows in series through the

transformer primary and the switch is sensed by a resistor

connected between the source of the switch and GND. If

the voltage across this resistor exceeds 300mV, the

LTC3725 initiates a fault.

Voltage Feedforward

The LTC3725 uses voltage feedforward to properly modu-

late the duty cycle as a function of the input voltage. For

secondary-side control with the LTC3706, voltage

feedforward is used during start-up only. The duty cycle

during start up is determined by comparison of the voltage

on the SSFLT pin to a 75% duty cycle triangle wave with

an amplitude of 2V. To implement voltage feedforward, the

charging current for the soft-start capacitor is reduced in

proportion to the input voltage. As a result, the initial rate

of rise of the converter output voltage is held approxi-

mately constant regardless of the input voltage. At some

point during start-up, the LTC3706 begins to switch the

pulse transformer and take over the soft-start.

For operation with standalone primary-side control and

optoisolator feedback, voltage feedforward is used during

both start-up and normal operation. The duty cycle is

determined by using a 75% duty cycle triangle wave with

an amplitude equal to 66% of the voltage on the UVLO pin

which is, in turn, proportional to V

. The charging current

for the soft-start capacitor is a constant 5.2µA. During

soft-start, the duty cycle is determined by comparing the

voltage on the SSFLT pin to the triangle wave. Soft-start is

concluded when the voltage on the SSFLT pin exceeds the

voltage on the FB/IN

pin. After the conclusion of soft-

start, the duty cycle is determined by comparison of the

voltage on the FB/IN

pin to the triangle wave.

Optoisolator Bias

When the LTC3725 is used in standalone primary-side

mode, feedback is provided by an optoisolator connected

to the FB/IN

pin. The LTC3725 has a built optoisolator

bias circuit which eliminates the need for external

components.

OPERATIO

LTC3725

3725fa

Note that a trickle charger usually requires a large capaci-

tor to provide holdup for the V

pin while the converter

attempts to start. The linear regulator in the LTC3725 can

both charge the capacitor connected to the V

pin and

provide primary-side gate-drive bias current. Therefore,

with the linear regulator, the capacitor need only be large

enough to cope with the ripple current from driving the gate

of the primary FET and holdup need not be considered.

The external NMOS for the linear regulator should be a

standard 3V threshold type (i.e. not a logic level thresh-

old). The rate of charge of V

from 0V to 8V is controlled

by the LTC3725 to be approximately 45µs regardless of

the size of the capacitor connected to the V

pin. The

charging current for this capacitor is approximately:

The safe operating area (SOA) for the external NMOS

should be chosen so that capacitor charging does not

damage the NMOS. Excessive values of capacitor are

unnecessary and should be avoided.

Start-Up Considerations

When used in a self-starting converter with the LTC3706,

the LTC3725 initially begins the soft-start of the converter

in an open-loop fashion. After bias is obtained on the

secondary side, the LTC3706 assumes control and com-

pletes the soft-start interval. In order to ensure that control

is properly transferred from the LTC3725 (primary-side)

to the LTC3706 (secondary-side), it is necessary to limit

the rate of rise on the primary-side soft-start ramp so that

the LTC3706 has adequate time to wake up and assume

control before the output voltage gets too high. This

condition is satisfied for many applications if the following

relationship is maintained:

SS,SEC

≤ C

SS_PRI

APPLICATIO S I FOR ATIO

WUU

Figure 2. Resistive Voltage Divider for

UVLO and Optional Run/Stop Control

UVLO

The UVLO pin is connected to a resistive voltage divider

connected to V

as shown in Figure 2. The voltage

threshold on the UVLO pin for V

rising is 1.242V. To

introduce hysteresis, the LTC3725 draws 4.9µA from the

UVLO pin when V

is rising. The hysteresis is therefore

user adjustable and depends on the value of R1. The UVLO

threshold for V

rising is:

IN UVLO RISING(, )

(. ) (. )=

+µ1 242

149

The LTC3725 also has 16mV of voltage hysteresis on the

UVLO pin so that the UVLO threshold for V

falling is:

IN UVLO FALLING(, )

(. )=

1 226

To implement external Run/Stop control, connect a small

NMOS to the UVLO pin as shown in Figure 2. Turning the

NMOS on grounds the UVLO pin and prevents the LTC3725

from running.

RUN/STOP

CONTROL

(OPTIONAL)

UVLO

GND

LTC3725

3725 F02

Linear Regulator

The linear regulator eliminates the long start-up times

associated with a conventional trickle charger by using an

external NMOS to quickly charge the capacitor connected

to the V

pin.

LTC3725

3725fa

However, care should be taken to ensure that soft-start

transfer from primary-side to secondary-side is com-

pleted well before the output voltage reaches its target

value. A good design goal is to have the transfer completed

when the output voltage is less than one-half of its target

value. Note that the fastest output voltage rise time during

primary-side soft-start mode occurs with minimum load

current.

The open-loop start-up frequency on the LTC3725 is set

by placing a resistor R

FS(S)

from the FS/IN

–

pin to GND.

Although the exact start-up frequency on the primary side

is not critical, it is generally a good practice to set it

approximately equal to the operating frequency on the

secondary side.

In this mode the start-up frequency of the LTC3725 is

approximately:

PRI

FS S

34 10

10 000

•

()

In the event that the LTC3706 fails to start up properly and

assume control of switching, there are several fail-safe

mechanisms to help avoid overvoltage conditions. First,

the LTC3725 implements a volt-second clamp that may be

used to keep the primary-side duty cycle at a level that

does not produce an excessive output voltage. Second,

the timeout of the linear regulator (described in the follow-

ing section) means that, unless the LTC3706 starts and

supports the LTC3725 gate drive through the pulse trans-

former and on-chip rectifier, the LTC3725 eventually suf-

fers a gate drive undervoltage fault. Finally, the LTC3706

has an independent overvoltage detection circuit that

crowbars the output of the DC/DC converter using the

synchronous secondary-side MOSFET switch.

In the event that a short-circuit is applied to the output of

the converter prior to start-up, the LTC3706 generally

does not receive enough bias voltage to operate. In this

case, the LTC3725 detects a FAULT for one of two reasons:

1) since the LTC3706 never sends pulse encoding to the

LTC3725, the linear regulator times out resulting in a gate

drive undervoltage fault, or 2) the primary-side overcurrent

circuit is tripped because of current buildup in the output

inductor. In either case, the LTC3725 initiates a shutdown

followed by a soft-start retry.

Linear Regulator Timeout

After start-up, the LTC3725 times out the linear regulator

to prevent overheating of the external NMOS. The timeout

interval is set by further charging the soft-start capacitor

SSFLT

from the end-of-soft-start voltage of approximately

2.8V to the timeout threshold of 3.9V. Linear regulator

timeout behaves differently depending on mode.

In primary-side standalone mode, the LTC3725 generally

requires that an auxiliary gate drive bias supply take over

from the linear regulator. (See the subsequent section for

more detail on the auxiliary supply.) During linear regula-

tor timeout, the rate of rise of the soft-start capacitor

voltage depends on the current into the NDRV pin as

controlled by the pull-up resistor R

PULLUP

, the value of V

and the value of V

NDRV

IN NDRV

PULLUP

–

The value of V

NDRV

is V

= 8V plus the value of the gate-

to-source voltage (V

NDRV

– V

) of the external NMOS in

the linear regulator. The gate-to-source voltage depends

on the actual device but is approximately the threshold

voltage of the external NMOS.

For I

NDRV

> 0.27mA, the capacitor on the SSFLT pin is

charged in proportion to (I

NDRV

– 0.27mA) until the linear

regulator times out. Thus, since V

NDRV

is very nearly

constant, the timeout interval for the linear regulator is

inversely proportional to the input voltage and a higher

input voltage produces a shorter timeout.

CVV

TIMEOUT

SSFLT

IN NDRV

PULLUP

−

⎡

⎣

⎢

⎤

⎦

⎥

66 39 28

027

(. – . )

–.

APPLICATIO S I FOR ATIO

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LTC3725EMSE#TRPBF

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Switching Voltage Regulators Primary Side Controller

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